riscv: add mseccfgh register

Adds the `mseccfgh` machine security configuration (high-bits) CSR.

Author: rmsyn

riscv/src/register.rs

@@ -114,6 +114,8 @@ pub use self::mhpmeventx::*;
 // Machine configuration
 pub mod mconfigptr;
 pub mod mseccfg;
+#[cfg(any(test, target_arch = "riscv32"))]
+pub mod mseccfgh;
 
 #[cfg(test)]
 mod tests;

riscv/src/register/mseccfgh.rs

@@ -0,0 +1,20 @@
+//! mseccfgh register
+
+use super::mseccfg::PMM;
+
+read_write_csr! {
+    /// mseccfgh register
+    Mseccfgh: 0x757,
+    mask: 0x3,
+}
+
+read_write_csr_field! {
+    Mseccfgh,
+    /// Pointer Masking Machine-mode
+    ///
+    /// # Note
+    ///
+    /// Defined in in the [Smmpm](https://github.com/riscv/riscv-j-extension/releases/download/pointer-masking-ratified/pointer-masking-ratified.pdf) extension.
+    pmm,
+    PMM: [0:1],
+}