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Merge #15
15: Refactoring: use new macros for M-mode CSRs r=dvc94ch a=Disasm Co-authored-by: Vadim Kaushan <[email protected]>
2 parents 8bffbd7 + 52ad774 commit 86ac78b

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15 files changed

+64
-312
lines changed

15 files changed

+64
-312
lines changed

‎src/register/macros.rs

Lines changed: 32 additions & 0 deletions
Original file line numberDiff line numberDiff line change
@@ -17,6 +17,25 @@ macro_rules! read_csr {
1717
};
1818
}
1919

20+
macro_rules! read_csr_rv32 {
21+
($csr_number:expr) => {
22+
/// Reads the CSR
23+
#[inline]
24+
#[cfg(target_arch = "riscv32")]
25+
unsafe fn _read() -> usize {
26+
let r: usize;
27+
asm!("csrrs $0, $1, x0" : "=r"(r) : "i"($csr_number) :: "volatile");
28+
r
29+
}
30+
31+
#[inline]
32+
#[cfg(not(target_arch = "riscv32"))]
33+
unsafe fn _read() -> usize {
34+
unimplemented!()
35+
}
36+
};
37+
}
38+
2039
macro_rules! read_csr_as {
2140
($register:ident, $csr_number:expr) => {
2241
read_csr!($csr_number);
@@ -28,6 +47,7 @@ macro_rules! read_csr_as {
2847
}
2948
};
3049
}
50+
3151
macro_rules! read_csr_as_usize {
3252
($csr_number:expr) => {
3353
read_csr!($csr_number);
@@ -40,6 +60,18 @@ macro_rules! read_csr_as_usize {
4060
};
4161
}
4262

63+
macro_rules! read_csr_as_usize_rv32 {
64+
($csr_number:expr) => {
65+
read_csr_rv32!($csr_number);
66+
67+
/// Reads the CSR
68+
#[inline]
69+
pub fn read() -> usize {
70+
unsafe{ _read() }
71+
}
72+
};
73+
}
74+
4375
macro_rules! write_csr {
4476
($csr_number:expr) => {
4577
/// Writes the CSR

‎src/register/mcause.rs

Lines changed: 1 addition & 16 deletions
Original file line numberDiff line numberDiff line change
@@ -136,19 +136,4 @@ impl Mcause {
136136
}
137137
}
138138

139-
/// Reads the CSR
140-
#[inline]
141-
pub fn read() -> Mcause {
142-
match () {
143-
#[cfg(any(target_arch = "riscv32", target_arch = "riscv64"))]
144-
() => {
145-
let r: usize;
146-
unsafe {
147-
asm!("csrrs $0, 0x342, x0" : "=r"(r) ::: "volatile");
148-
}
149-
Mcause { bits: r }
150-
}
151-
#[cfg(not(any(target_arch = "riscv32", target_arch = "riscv64")))]
152-
() => unimplemented!(),
153-
}
154-
}
139+
read_csr_as!(Mcause, 0x342);

‎src/register/mcycle.rs

Lines changed: 1 addition & 16 deletions
Original file line numberDiff line numberDiff line change
@@ -1,18 +1,3 @@
11
//! mcycle register
22
3-
/// Reads the CSR
4-
#[inline]
5-
pub fn read() -> usize {
6-
match () {
7-
#[cfg(any(target_arch = "riscv32", target_arch = "riscv64"))]
8-
() => {
9-
let r: usize;
10-
unsafe {
11-
asm!("csrrs $0, 0xB00, x0" : "=r"(r) ::: "volatile");
12-
}
13-
r
14-
}
15-
#[cfg(not(any(target_arch = "riscv32", target_arch = "riscv64")))]
16-
() => unimplemented!(),
17-
}
18-
}
3+
read_csr_as_usize!(0xB00);

‎src/register/mcycleh.rs

Lines changed: 1 addition & 16 deletions
Original file line numberDiff line numberDiff line change
@@ -1,18 +1,3 @@
11
//! mcycleh register
22
3-
/// Reads the CSR
4-
#[inline]
5-
pub fn read() -> usize {
6-
match () {
7-
#[cfg(target_arch = "riscv32")]
8-
() => {
9-
let r: usize;
10-
unsafe {
11-
asm!("csrrs $0, 0xB80, x0" : "=r"(r) ::: "volatile");
12-
}
13-
r
14-
}
15-
#[cfg(not(target_arch = "riscv32"))]
16-
() => unimplemented!(),
17-
}
18-
}
3+
read_csr_as_usize_rv32!(0xB80);

‎src/register/mepc.rs

Lines changed: 1 addition & 16 deletions
Original file line numberDiff line numberDiff line change
@@ -1,18 +1,3 @@
11
//! mepc register
22
3-
/// Reads the CSR
4-
#[inline]
5-
pub fn read() -> usize {
6-
match () {
7-
#[cfg(any(target_arch = "riscv32", target_arch = "riscv64"))]
8-
() => {
9-
let r: usize;
10-
unsafe {
11-
asm!("csrrs $0, 0x341, x0" : "=r"(r) ::: "volatile");
12-
}
13-
r
14-
},
15-
#[cfg(not(any(target_arch = "riscv32", target_arch = "riscv64")))]
16-
() => unimplemented!(),
17-
}
18-
}
3+
read_csr_as_usize!(0x341);

‎src/register/mie.rs

Lines changed: 3 additions & 65 deletions
Original file line numberDiff line numberDiff line change
@@ -68,71 +68,9 @@ impl Mie {
6868
}
6969
}
7070

71-
/// Reads the CSR
72-
#[inline]
73-
pub fn read() -> Mie {
74-
match () {
75-
#[cfg(any(target_arch = "riscv32", target_arch = "riscv64"))]
76-
() => {
77-
let r: usize;
78-
unsafe {
79-
asm!("csrrs $0, 0x304, x0" : "=r"(r) ::: "volatile");
80-
}
81-
Mie { bits: r }
82-
}
83-
#[cfg(not(any(target_arch = "riscv32", target_arch = "riscv64")))]
84-
() => unimplemented!(),
85-
}
86-
}
87-
88-
/// Sets the CSR
89-
#[cfg_attr(not(any(target_arch = "riscv32", target_arch = "riscv64")), allow(unused_variables))]
90-
#[inline]
91-
unsafe fn set(bits: usize) {
92-
match () {
93-
#[cfg(any(target_arch = "riscv32", target_arch = "riscv64"))]
94-
() => asm!("csrrs x0, 0x304, $0" :: "r"(bits) :: "volatile"),
95-
#[cfg(not(any(target_arch = "riscv32", target_arch = "riscv64")))]
96-
() => unimplemented!(),
97-
}
98-
}
99-
100-
/// Clears the CSR
101-
#[cfg_attr(not(any(target_arch = "riscv32", target_arch = "riscv64")), allow(unused_variables))]
102-
#[inline]
103-
unsafe fn clear(bits: usize) {
104-
match () {
105-
#[cfg(any(target_arch = "riscv32", target_arch = "riscv64"))]
106-
() => asm!("csrrc x0, 0x304, $0" :: "r"(bits) :: "volatile"),
107-
#[cfg(not(any(target_arch = "riscv32", target_arch = "riscv64")))]
108-
() => unimplemented!(),
109-
}
110-
}
111-
112-
macro_rules! set_csr {
113-
($set_field:ident, $e:expr) => {
114-
#[inline]
115-
pub unsafe fn $set_field() {
116-
set($e);
117-
}
118-
}
119-
}
120-
121-
macro_rules! clear_csr {
122-
($clear_field:ident, $e:expr) => {
123-
#[inline]
124-
pub unsafe fn $clear_field() {
125-
clear($e);
126-
}
127-
}
128-
}
129-
130-
macro_rules! set_clear_csr {
131-
($set_field:ident, $clear_field:ident, $e:expr) => {
132-
set_csr!($set_field, $e);
133-
clear_csr!($clear_field, $e);
134-
}
135-
}
71+
read_csr_as!(Mie, 0x304);
72+
set!(0x304);
73+
clear!(0x304);
13674

13775
/// User Software Interrupt Enable
13876
set_clear_csr!(set_usoft, clear_usoft, 1 << 0);

‎src/register/minstret.rs

Lines changed: 1 addition & 16 deletions
Original file line numberDiff line numberDiff line change
@@ -1,18 +1,3 @@
11
//! minstret register
22
3-
/// Reads the CSR
4-
#[inline]
5-
pub fn read() -> usize {
6-
match () {
7-
#[cfg(any(target_arch = "riscv32", target_arch = "riscv64"))]
8-
() => {
9-
let r: usize;
10-
unsafe {
11-
asm!("csrrs $0, 0xB02, x0" : "=r"(r) ::: "volatile");
12-
}
13-
r
14-
}
15-
#[cfg(not(any(target_arch = "riscv32", target_arch = "riscv64")))]
16-
() => unimplemented!(),
17-
}
18-
}
3+
read_csr_as_usize!(0xB02);

‎src/register/minstreth.rs

Lines changed: 1 addition & 16 deletions
Original file line numberDiff line numberDiff line change
@@ -1,18 +1,3 @@
11
//! minstreth register
22
3-
/// Reads the CSR
4-
#[inline]
5-
pub fn read() -> usize {
6-
match () {
7-
#[cfg(target_arch = "riscv32")]
8-
() => {
9-
let r: usize;
10-
unsafe {
11-
asm!("csrrs $0, 0xB82, x0" : "=r"(r) ::: "volatile");
12-
}
13-
r
14-
},
15-
#[cfg(not(target_arch = "riscv32"))]
16-
() => unimplemented!(),
17-
}
18-
}
3+
read_csr_as_usize_rv32!(0xB82);

‎src/register/mip.rs

Lines changed: 1 addition & 16 deletions
Original file line numberDiff line numberDiff line change
@@ -68,19 +68,4 @@ impl Mip {
6868
}
6969
}
7070

71-
/// Reads the CSR
72-
#[inline]
73-
pub fn read() -> Mip {
74-
match () {
75-
#[cfg(any(target_arch = "riscv32", target_arch = "riscv64"))]
76-
() => {
77-
let r: usize;
78-
unsafe {
79-
asm!("csrrs $0, 0x344, x0" : "=r"(r) ::: "volatile");
80-
}
81-
Mip { bits: r }
82-
}
83-
#[cfg(not(any(target_arch = "riscv32", target_arch = "riscv64")))]
84-
() => unimplemented!(),
85-
}
86-
}
71+
read_csr_as!(Mip, 0x344);

‎src/register/misa.rs

Lines changed: 6 additions & 14 deletions
Original file line numberDiff line numberDiff line change
@@ -47,21 +47,13 @@ impl Misa {
4747
}
4848
}
4949

50+
read_csr!(0x301);
51+
5052
/// Reads the CSR
5153
#[inline]
5254
pub fn read() -> Option<Misa> {
53-
match () {
54-
#[cfg(any(target_arch = "riscv32", target_arch = "riscv64"))]
55-
() => {
56-
let r: usize;
57-
unsafe {
58-
asm!("csrrs $0, 0x301, x0" : "=r"(r) ::: "volatile");
59-
}
60-
// When misa is hardwired to zero it means that the misa csr
61-
// isn't implemented.
62-
NonZeroUsize::new(r).map(|bits| Misa { bits })
63-
},
64-
#[cfg(not(any(target_arch = "riscv32", target_arch = "riscv64")))]
65-
() => unimplemented!(),
66-
}
55+
let r = unsafe{ _read() };
56+
// When misa is hardwired to zero it means that the misa csr
57+
// isn't implemented.
58+
NonZeroUsize::new(r).map(|bits| Misa { bits })
6759
}

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