Merge pull request #332 from bjoernQ/support-chips-wo-mie-mip

Support chips which don't support MIE/MIP CSRs

Author: romancardenas

riscv-rt/CHANGELOG.md

@@ -13,6 +13,7 @@ and this project adheres to [Semantic Versioning](http://semver.org/).
 - New `#[riscv_rt::post_init]` attribute to aid in the definition of the `__post_init` function. 
 - Added `.uninit` section to the linker file. Due to its similarities with `.bss`, the
   linker will place this new section in `REGION_BSS`.
+- Additional feature `no-xie-xip` to work on chips without the XIE and XIP CSRs (e.g. ESP32-C2, ESP32-C3)
 
 ### Changed
 

riscv-rt/Cargo.toml

@@ -40,5 +40,6 @@ v-trap = ["riscv-rt-macros/v-trap"]
 u-boot = ["riscv-rt-macros/u-boot", "single-hart"]
 no-interrupts = []
 no-exceptions = []
+no-xie-xip = []
 device = []
 memory = []

riscv-rt/src/asm.rs

@@ -65,13 +65,14 @@ _abs_start:
     .cfi_startproc
     .cfi_undefined ra",
     // Disable interrupts
-    #[cfg(feature = "s-mode")]
+    #[cfg(all(feature = "s-mode", not(feature = "no-xie-xip")))]
     "csrw sie, 0
     csrw sip, 0",
-    #[cfg(not(feature = "s-mode"))]
+    #[cfg(all(not(feature = "s-mode"), not(feature = "no-xie-xip")))]
     "csrw mie, 0
-    csrw mip, 0
-    csrr a0, mhartid", // Make sure that the hart ID is in a0 in M-mode
+    csrw mip, 0",
+    #[cfg(not(feature = "s-mode"))]
+    "csrr a0, mhartid", // Make sure that the hart ID is in a0 in M-mode
     // Set pre-init trap vector
     "la t0, _pre_init_trap",
     #[cfg(feature = "s-mode")]