riscv v0.15.0

A new batch of RISC-V releases is now available at crates.io! Here we enumerate the most important changes, but please read the CHANGELOG.md files for further details.

riscv v0.15.0

• @rmsyn added proxies to new CSRs.
• @romancardenas added new methods and associated functions that rely on riscv-pac abstractions for interrupts.
• @jsgf fixed a bug with the mcause bit mask.

riscv-peripheral v0.4.0

• @romancardenas added new constant methods to access registers for HART 0.

riscv-rt v0.16.0

This release features numerous exciting changes. The most important are:

• @bjoernQ added the final necessary changes to allow esp-riscv-rt to run on top of riscv-rt.
• @romancardenas added linker sections and adapted the boot process to resemble cortex-m-rt and esp-riscv-rt.
• @janderholm fixed a bug in the linker file. Also, the stack is now split into equal parts based on the number of hearts. In addition, the runtime now avoids some relative jumps to ease the linker placement of code.
• @jannic and @Dirbaio merged global_asm macro invocations to avoid potential undefined behavior in future Rust releases.

Other changes

• @Lumilesto fixed some links in the docs
• @gibbz00 improved the CI process with spelling checks and improved the docs of riscv-rt

Thank you to all the people who contributed to these releases!