riscv 0.13.0

riscv 0.12.0

• CSR writes are now all unsafe. Users can open an RFC to nominate certain CSRs to be safe (#209)
• All CSR fields are now generated using macros (thanks, @rmsyn !)
• PACs can now use the RISCV_MTVEC_ALIGN environment variable to set the vector table byte alignment ((thanks, @ia0 !)

riscv-rt 0.13.0

• Compatibility with RV32E and RV64E!
• Linker script is now more aligned with cortex-m-rt

riscv-target-parser 0.1.0

New utility crate to assist in build scripts of the RISC-V ecosystem. It is useful for determining which extensions are available, the base ISA of the target, etc.

riscv-peripheral 0.2.1 and riscv-semihosting 0.1.3

Update dependencies