feat(09): Implement RP1 GPIO driver

Adds the GPIO driver for the Raspberry Pi 5's RP1 I/O controller.

The RP1 requires a two-step GPIO setup for peripherals. This driver handles the logic for both the PADS_BANK0 and IO_BANK0 register blocks.

The build system is modified to conditionally compile this driver when the 'bsp_rpi5' feature is enabled.

Author: devansh-lodha

09_privilege_level/src/bsp/device_driver.rs

@@ -1,12 +1,24 @@
 // SPDX-License-Identifier: MIT OR Apache-2.0
 //
-// Copyright (c) 2018-2023 Andre Richter <[email protected]>
+// Copyright (c) 2018-2025 Andre Richter <[email protected]>
 
 //! Device driver.
 
-#[cfg(any(feature = "bsp_rpi3", feature = "bsp_rpi4"))]
+#[cfg(any(feature = "bsp_rpi3", feature = "bsp_rpi4", feature = "bsp_rpi5"))]
 mod bcm;
+#[cfg(feature = "bsp_rpi5")]
+mod rp1_gpio;
+
 mod common;
 
+// For RPi3 and RPi4, re-export everything from the `bcm` module, which includes
+// both the GPIO and UART drivers.
 #[cfg(any(feature = "bsp_rpi3", feature = "bsp_rpi4"))]
 pub use bcm::*;
+
+// For RPi5, re-export only the drivers it uses: the common PL011Uart from the bcm
+// module and its specific GPIO driver from the rp1_gpio module.
+#[cfg(feature = "bsp_rpi5")]
+pub use bcm::PL011Uart;
+#[cfg(feature = "bsp_rpi5")]
+pub use rp1_gpio::GPIO;

09_privilege_level/src/bsp/device_driver/bcm.rs

@@ -1,11 +1,19 @@
 // SPDX-License-Identifier: MIT OR Apache-2.0
 //
-// Copyright (c) 2018-2023 Andre Richter <[email protected]>
+// Copyright (c) 2018-2025 Andre Richter <[email protected]>
 
 //! BCM driver top level.
 
+// The bcm2xxx_gpio driver is only for RPi3 and RPi4.
+#[cfg(any(feature = "bsp_rpi3", feature = "bsp_rpi4"))]
 mod bcm2xxx_gpio;
+
+// The PL011 UART is used by all supported RPi versions.
 mod bcm2xxx_pl011_uart;
 
+// Re-export the GPIO driver only for RPi3 and RPi4.
+#[cfg(any(feature = "bsp_rpi3", feature = "bsp_rpi4"))]
 pub use bcm2xxx_gpio::*;
+
+// Re-export the UART driver for all.
 pub use bcm2xxx_pl011_uart::*;

09_privilege_level/src/bsp/device_driver/rp1_gpio.rs

@@ -0,0 +1,166 @@
+// SPDX-License-Identifier: MIT OR Apache-2.0
+//
+// Copyright (c) 2025 Devansh Lodha <[email protected]>
+// Copyright (c) 2018-2025 Andre Richter <[email protected]>
+
+//! RP1 GPIO Driver for Raspberry Pi 5.
+
+use crate::{
+    bsp::device_driver::common::MMIODerefWrapper, driver, synchronization,
+    synchronization::NullLock,
+};
+use tock_registers::{
+    interfaces::{Readable, Writeable},
+    register_structs,
+    registers::ReadWrite,
+};
+
+//--------------------------------------------------------------------------------------------------
+// Private Definitions
+//--------------------------------------------------------------------------------------------------
+
+// Describes the layout of the IO_BANK0 registers.
+// Found in the "RP1 Peripherals" datasheet, section 3.1.4, Table 6.
+register_structs! {
+    #[allow(non_snake_case)]
+    IoBank0RegisterBlock {
+        (0x000 => _reserved1),
+        (0x074 => GPIO14_CTRL: ReadWrite<u32>), // GPIO 14 Control Register
+        (0x078 => _reserved2),
+        (0x07c => GPIO15_CTRL: ReadWrite<u32>), // GPIO 15 Control Register
+        (0x080 => @END),
+    }
+}
+
+// Describes the layout of the PADS_BANK0 registers.
+// Found in the "RP1 Peripherals" datasheet, section 3.1.4, Table 19.
+register_structs! {
+    #[allow(non_snake_case)]
+    PadsBank0RegisterBlock {
+        (0x000 => _reserved1),
+        (0x03c => GPIO14: ReadWrite<u32>),      // Pad control for GPIO 14
+        (0x040 => GPIO15: ReadWrite<u32>),      // Pad control for GPIO 15
+        (0x044 => @END),
+    }
+}
+
+/// Abstraction for the IO_BANK0 registers.
+type IoBank0Registers = MMIODerefWrapper<IoBank0RegisterBlock>;
+
+/// Abstraction for the PADS_BANK0 registers.
+type PadsBank0Registers = MMIODerefWrapper<PadsBank0RegisterBlock>;
+
+// The inner state of the GPIO driver.
+struct GPIOInner {
+    io_bank0: IoBank0Registers,
+    pads_bank0: PadsBank0Registers,
+}
+
+//--------------------------------------------------------------------------------------------------
+// Public Definitions
+//--------------------------------------------------------------------------------------------------
+
+/// Representation of the GPIO peripheral.
+pub struct GPIO {
+    inner: NullLock<GPIOInner>,
+}
+
+//--------------------------------------------------------------------------------------------------
+// Implementation
+//--------------------------------------------------------------------------------------------------
+
+impl GPIOInner {
+    /// Create an instance.
+    ///
+    /// # Safety
+    ///
+    /// - The user must ensure to provide correct MMIO start addresses.
+    pub const unsafe fn new(
+        io_bank0_mmio_start_addr: usize,
+        pads_bank0_mmio_start_addr: usize,
+    ) -> Self {
+        Self {
+            io_bank0: IoBank0Registers::new(io_bank0_mmio_start_addr),
+            pads_bank0: PadsBank0Registers::new(pads_bank0_mmio_start_addr),
+        }
+    }
+
+    /// Map PL011 UART to GPIO pins 14 and 15.
+    pub fn map_pl011_uart(&mut self) {
+        // From RP1 Peripherals datasheet, Table 21: PADS_BANK0 GPIO0 Register
+        const BIT_PADS_OD: u32 = 1 << 7;  // Output Disable
+        const BIT_PADS_IE: u32 = 1 << 6;  // Input Enable
+        const BIT_PADS_PUE: u32 = 1 << 3; // Pull-Up Enable
+
+        // From RP1 Peripherals datasheet, Table 4: GPIO function selection
+        const FUNCSEL_FIELD_LSB: u32 = 0;
+        const FUNCSEL_FIELD_MASK: u32 = 0x1F << FUNCSEL_FIELD_LSB;
+        const FUNC_UART0: u32 = 4; // UART0 is alternate function 4
+
+        // --- Configure GPIO 14 as UART0 TX ---
+
+        // 1. Set pad electrical properties in PADS_BANK0.
+        //    - Clear Output Disable (OD) bit to enable output.
+        let mut pads14_val = self.pads_bank0.GPIO14.get();
+        pads14_val &= !BIT_PADS_OD;
+        self.pads_bank0.GPIO14.set(pads14_val);
+
+        // 2. Set pin function in IO_BANK0.
+        let mut io14_val = self.io_bank0.GPIO14_CTRL.get();
+        io14_val &= !FUNCSEL_FIELD_MASK; // Clear the function field.
+        io14_val |= FUNC_UART0 << FUNCSEL_FIELD_LSB; // Set to UART0.
+        self.io_bank0.GPIO14_CTRL.set(io14_val);
+
+        // --- Configure GPIO 15 as UART0 RX ---
+
+        // 1. Set pad electrical properties.
+        //    - Set Input Enable (IE) bit.
+        //    - Set Pull-Up Enable (PUE) as per datasheet recommendation.
+        let mut pads15_val = self.pads_bank0.GPIO15.get();
+        pads15_val |= BIT_PADS_IE | BIT_PADS_PUE;
+        self.pads_bank0.GPIO15.set(pads15_val);
+
+        // 2. Set pin function.
+        let mut io15_val = self.io_bank0.GPIO15_CTRL.get();
+        io15_val &= !FUNCSEL_FIELD_MASK; // Clear the function field.
+        io15_val |= FUNC_UART0 << FUNCSEL_FIELD_LSB; // Set to UART0.
+        self.io_bank0.GPIO15_CTRL.set(io15_val);
+    }
+}
+
+impl GPIO {
+    pub const COMPATIBLE: &'static str = "RP1 GPIO";
+
+    /// Create an instance.
+    ///
+    /// # Safety
+    ///
+    /// - The user must ensure to provide correct MMIO start addresses for both register blocks.
+    pub const unsafe fn new(
+        io_bank0_mmio_start_addr: usize,
+        pads_bank0_mmio_start_addr: usize,
+    ) -> Self {
+        Self {
+            inner: NullLock::new(GPIOInner::new(
+                io_bank0_mmio_start_addr,
+                pads_bank0_mmio_start_addr,
+            )),
+        }
+    }
+
+    /// Concurrency-safe version of `GPIOInner.map_pl011_uart()`.
+    pub fn map_pl011_uart(&self) {
+        self.inner.lock(|inner| inner.map_pl011_uart())
+    }
+}
+
+//------------------------------------------------------------------------------
+// OS Interface Code
+//------------------------------------------------------------------------------
+use synchronization::interface::Mutex;
+
+impl driver::interface::DeviceDriver for GPIO {
+    fn compatible(&self) -> &'static str {
+        Self::COMPATIBLE
+    }
+}