Prereleased 2025-08-15
Pre-release
Pre-release
·
577 commits
to master
since this release
- Fix new
mismatched-lifetime-syntaxes
lint warnings - Adapt RISC-V specific codegen for
riscv-peripheral
v0.3.0 rework - Include
riscv-peripheral
peripherals inPeripherals
struct repr(transparent)
for field wrapper- Ensure
__INTERRUPTS
are#[no_mangle]
on Xtensa. - Add
base_isa
field toriscv_config
to allow theriscv_rt::core_interrupt
macro to properly generate start trap assembly routines in vectored mode. - Add
edition
flag