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fhahn
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[LV] Don't run instcombine for interleaved-accesses test.
Drop instcombine from the run-line to make test independent and make it easier to follow the generated code for SCEV predicate checks. (cherry picked from commit ec581e4)
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‎llvm/test/Transforms/LoopVectorize/interleaved-accesses-requiring-scev-predicates.ll‎

Lines changed: 32 additions & 25 deletions
Original file line numberDiff line numberDiff line change
@@ -1,5 +1,5 @@
11
; NOTE: Assertions have been autogenerated by utils/update_test_checks.py UTC_ARGS: --check-globals none --version 5
2-
; RUN: opt -S -passes=loop-vectorize,instcombine -force-vector-width=4 -force-vector-interleave=1 -enable-interleaved-mem-accesses=true < %s | FileCheck %s
2+
; RUN: opt -S -passes=loop-vectorize -force-vector-width=4 -force-vector-interleave=1 -enable-interleaved-mem-accesses=true %s | FileCheck %s
33

44
target datalayout = "e-m:e-i64:64-f80:128-n8:16:32:64-S128"
55

@@ -29,38 +29,42 @@ define void @wrap_around_scev_check(ptr noalias %a, ptr noalias %b, i8 %x, i8 %y
2929
; CHECK-NEXT: br i1 [[CMP9]], label %[[EXIT:.*]], label %[[LOOP_PREHEADER:.*]]
3030
; CHECK: [[LOOP_PREHEADER]]:
3131
; CHECK-NEXT: [[WIDE_TRIP_COUNT:%.*]] = zext i8 [[Y]] to i64
32-
; CHECK-NEXT: [[MIN_ITERS_CHECK:%.*]] = icmp ult i8 [[Y]], 5
32+
; CHECK-NEXT: [[MIN_ITERS_CHECK:%.*]] = icmp ule i64 [[WIDE_TRIP_COUNT]], 4
3333
; CHECK-NEXT: br i1 [[MIN_ITERS_CHECK]], label %[[SCALAR_PH:.*]], label %[[VECTOR_SCEVCHECK:.*]]
3434
; CHECK: [[VECTOR_SCEVCHECK]]:
3535
; CHECK-NEXT: [[TMP0:%.*]] = add nsw i64 [[WIDE_TRIP_COUNT]], -1
3636
; CHECK-NEXT: [[TMP1:%.*]] = trunc i64 [[TMP0]] to i8
37-
; CHECK-NEXT: [[MUL_RESULT:%.*]] = shl i8 [[TMP1]], 1
38-
; CHECK-NEXT: [[TMP2:%.*]] = xor i8 [[X]], -1
39-
; CHECK-NEXT: [[TMP3:%.*]] = icmp ugt i8 [[MUL_RESULT]], [[TMP2]]
40-
; CHECK-NEXT: [[TMP4:%.*]] = icmp ugt i64 [[TMP0]], 127
37+
; CHECK-NEXT: [[MUL1:%.*]] = call { i8, i1 } @llvm.umul.with.overflow.i8(i8 2, i8 [[TMP1]])
38+
; CHECK-NEXT: [[MUL_RESULT:%.*]] = extractvalue { i8, i1 } [[MUL1]], 0
39+
; CHECK-NEXT: [[TMP4:%.*]] = extractvalue { i8, i1 } [[MUL1]], 1
40+
; CHECK-NEXT: [[TMP2:%.*]] = add i8 [[X]], [[MUL_RESULT]]
41+
; CHECK-NEXT: [[TMP3:%.*]] = icmp ult i8 [[TMP2]], [[X]]
4142
; CHECK-NEXT: [[TMP5:%.*]] = or i1 [[TMP3]], [[TMP4]]
42-
; CHECK-NEXT: br i1 [[TMP5]], label %[[SCALAR_PH]], label %[[VECTOR_PH:.*]]
43+
; CHECK-NEXT: [[TMP17:%.*]] = icmp ugt i64 [[TMP0]], 255
44+
; CHECK-NEXT: [[TMP18:%.*]] = or i1 [[TMP5]], [[TMP17]]
45+
; CHECK-NEXT: br i1 [[TMP18]], label %[[SCALAR_PH]], label %[[VECTOR_PH:.*]]
4346
; CHECK: [[VECTOR_PH]]:
44-
; CHECK-NEXT: [[N_MOD_VF:%.*]] = and i64 [[WIDE_TRIP_COUNT]], 3
47+
; CHECK-NEXT: [[N_MOD_VF:%.*]] = urem i64 [[WIDE_TRIP_COUNT]], 4
4548
; CHECK-NEXT: [[TMP6:%.*]] = icmp eq i64 [[N_MOD_VF]], 0
4649
; CHECK-NEXT: [[TMP7:%.*]] = select i1 [[TMP6]], i64 4, i64 [[N_MOD_VF]]
47-
; CHECK-NEXT: [[N_VEC:%.*]] = sub nsw i64 [[WIDE_TRIP_COUNT]], [[TMP7]]
50+
; CHECK-NEXT: [[N_VEC:%.*]] = sub i64 [[WIDE_TRIP_COUNT]], [[TMP7]]
4851
; CHECK-NEXT: [[DOTCAST:%.*]] = trunc i64 [[N_VEC]] to i8
49-
; CHECK-NEXT: [[TMP8:%.*]] = shl i8 [[DOTCAST]], 1
52+
; CHECK-NEXT: [[TMP8:%.*]] = mul i8 [[DOTCAST]], 2
5053
; CHECK-NEXT: [[TMP9:%.*]] = add i8 [[X]], [[TMP8]]
5154
; CHECK-NEXT: br label %[[VECTOR_BODY:.*]]
5255
; CHECK: [[VECTOR_BODY]]:
5356
; CHECK-NEXT: [[INDEX:%.*]] = phi i64 [ 0, %[[VECTOR_PH]] ], [ [[INDEX_NEXT:%.*]], %[[VECTOR_BODY]] ]
5457
; CHECK-NEXT: [[DOTCAST2:%.*]] = trunc i64 [[INDEX]] to i8
55-
; CHECK-NEXT: [[TMP10:%.*]] = shl i8 [[DOTCAST2]], 1
58+
; CHECK-NEXT: [[TMP10:%.*]] = mul i8 [[DOTCAST2]], 2
5659
; CHECK-NEXT: [[OFFSET_IDX:%.*]] = add i8 [[X]], [[TMP10]]
5760
; CHECK-NEXT: [[TMP11:%.*]] = zext i8 [[OFFSET_IDX]] to i64
58-
; CHECK-NEXT: [[TMP12:%.*]] = getelementptr inbounds nuw i32, ptr [[A]], i64 [[TMP11]]
61+
; CHECK-NEXT: [[TMP12:%.*]] = getelementptr inbounds i32, ptr [[A]], i64 [[TMP11]]
5962
; CHECK-NEXT: [[WIDE_VEC:%.*]] = load <8 x i32>, ptr [[TMP12]], align 4
6063
; CHECK-NEXT: [[STRIDED_VEC:%.*]] = shufflevector <8 x i32> [[WIDE_VEC]], <8 x i32> poison, <4 x i32> <i32 0, i32 2, i32 4, i32 6>
6164
; CHECK-NEXT: [[TMP13:%.*]] = shl <4 x i32> [[STRIDED_VEC]], splat (i32 1)
6265
; CHECK-NEXT: [[TMP14:%.*]] = getelementptr inbounds i32, ptr [[B]], i64 [[INDEX]]
63-
; CHECK-NEXT: store <4 x i32> [[TMP13]], ptr [[TMP14]], align 4
66+
; CHECK-NEXT: [[TMP19:%.*]] = getelementptr inbounds i32, ptr [[TMP14]], i32 0
67+
; CHECK-NEXT: store <4 x i32> [[TMP13]], ptr [[TMP19]], align 4
6468
; CHECK-NEXT: [[INDEX_NEXT]] = add nuw i64 [[INDEX]], 4
6569
; CHECK-NEXT: [[TMP15:%.*]] = icmp eq i64 [[INDEX_NEXT]], [[N_VEC]]
6670
; CHECK-NEXT: br i1 [[TMP15]], label %[[MIDDLE_BLOCK:.*]], label %[[VECTOR_BODY]], !llvm.loop [[LOOP0:![0-9]+]]
@@ -74,7 +78,7 @@ define void @wrap_around_scev_check(ptr noalias %a, ptr noalias %b, i8 %x, i8 %y
7478
; CHECK-NEXT: [[IV:%.*]] = phi i64 [ [[BC_RESUME_VAL]], %[[SCALAR_PH]] ], [ [[IV_NEXT:%.*]], %[[LOOP]] ]
7579
; CHECK-NEXT: [[INDEX_011:%.*]] = phi i8 [ [[BC_RESUME_VAL3]], %[[SCALAR_PH]] ], [ [[ADD:%.*]], %[[LOOP]] ]
7680
; CHECK-NEXT: [[IDXPROM:%.*]] = zext i8 [[INDEX_011]] to i64
77-
; CHECK-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds nuw i32, ptr [[A]], i64 [[IDXPROM]]
81+
; CHECK-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds i32, ptr [[A]], i64 [[IDXPROM]]
7882
; CHECK-NEXT: [[TMP16:%.*]] = load i32, ptr [[ARRAYIDX]], align 4
7983
; CHECK-NEXT: [[MUL:%.*]] = shl i32 [[TMP16]], 1
8084
; CHECK-NEXT: [[ARRAYIDX2:%.*]] = getelementptr inbounds i32, ptr [[B]], i64 [[IV]]
@@ -120,28 +124,30 @@ exit:
120124
define void @wrap_predicate_for_interleave_group_wraps_for_known_trip_count(ptr noalias %x, ptr noalias %out) {
121125
; CHECK-LABEL: define void @wrap_predicate_for_interleave_group_wraps_for_known_trip_count(
122126
; CHECK-SAME: ptr noalias [[X:%.*]], ptr noalias [[OUT:%.*]]) {
123-
; CHECK-NEXT: [[START:.*:]]
127+
; CHECK-NEXT: [[START:.*]]:
124128
; CHECK-NEXT: br i1 false, label %[[SCALAR_PH:.*]], label %[[VECTOR_PH:.*]]
125129
; CHECK: [[VECTOR_PH]]:
126130
; CHECK-NEXT: br label %[[VECTOR_BODY:.*]]
127131
; CHECK: [[VECTOR_BODY]]:
128132
; CHECK-NEXT: [[INDEX:%.*]] = phi i64 [ 0, %[[VECTOR_PH]] ], [ [[INDEX_NEXT:%.*]], %[[VECTOR_BODY]] ]
129133
; CHECK-NEXT: [[TMP0:%.*]] = mul nuw nsw i64 [[INDEX]], 5
130-
; CHECK-NEXT: [[TMP1:%.*]] = and i64 [[TMP0]], 12
134+
; CHECK-NEXT: [[TMP1:%.*]] = and i64 [[TMP0]], 15
131135
; CHECK-NEXT: [[TMP2:%.*]] = getelementptr inbounds nuw i32, ptr [[X]], i64 [[TMP1]]
132136
; CHECK-NEXT: [[WIDE_VEC:%.*]] = load <20 x i32>, ptr [[TMP2]], align 4
133137
; CHECK-NEXT: [[STRIDED_VEC:%.*]] = shufflevector <20 x i32> [[WIDE_VEC]], <20 x i32> poison, <4 x i32> <i32 0, i32 5, i32 10, i32 15>
134138
; CHECK-NEXT: [[TMP3:%.*]] = getelementptr inbounds nuw i32, ptr [[OUT]], i64 [[INDEX]]
135-
; CHECK-NEXT: store <4 x i32> [[STRIDED_VEC]], ptr [[TMP3]], align 4
139+
; CHECK-NEXT: [[TMP5:%.*]] = getelementptr inbounds nuw i32, ptr [[TMP3]], i32 0
140+
; CHECK-NEXT: store <4 x i32> [[STRIDED_VEC]], ptr [[TMP5]], align 4
136141
; CHECK-NEXT: [[INDEX_NEXT]] = add nuw i64 [[INDEX]], 4
137142
; CHECK-NEXT: [[TMP4:%.*]] = icmp eq i64 [[INDEX_NEXT]], 12
138143
; CHECK-NEXT: br i1 [[TMP4]], label %[[MIDDLE_BLOCK:.*]], label %[[VECTOR_BODY]], !llvm.loop [[LOOP4:![0-9]+]]
139144
; CHECK: [[MIDDLE_BLOCK]]:
140145
; CHECK-NEXT: br label %[[SCALAR_PH]]
141146
; CHECK: [[SCALAR_PH]]:
147+
; CHECK-NEXT: [[BC_RESUME_VAL:%.*]] = phi i64 [ 12, %[[MIDDLE_BLOCK]] ], [ 0, %[[START]] ]
142148
; CHECK-NEXT: br label %[[LOOP:.*]]
143149
; CHECK: [[LOOP]]:
144-
; CHECK-NEXT: [[IV:%.*]] = phi i64 [ 12, %[[SCALAR_PH]] ], [ [[IV_NEXT:%.*]], %[[LOOP]] ]
150+
; CHECK-NEXT: [[IV:%.*]] = phi i64 [ [[BC_RESUME_VAL]], %[[SCALAR_PH]] ], [ [[IV_NEXT:%.*]], %[[LOOP]] ]
145151
; CHECK-NEXT: [[IV_NEXT]] = add nuw nsw i64 [[IV]], 1
146152
; CHECK-NEXT: [[IV_MUL5:%.*]] = mul nuw nsw i64 [[IV]], 5
147153
; CHECK-NEXT: [[IV_MUL5_MASKED:%.*]] = and i64 [[IV_MUL5]], 15
@@ -179,27 +185,28 @@ define void @wrap_predicate_for_interleave_group_unknown_trip_count(ptr noalias
179185
; CHECK-LABEL: define void @wrap_predicate_for_interleave_group_unknown_trip_count(
180186
; CHECK-SAME: ptr noalias [[X:%.*]], ptr noalias [[OUT:%.*]], i64 [[N:%.*]]) {
181187
; CHECK-NEXT: [[START:.*]]:
182-
; CHECK-NEXT: [[MIN_ITERS_CHECK:%.*]] = icmp ult i64 [[N]], 5
188+
; CHECK-NEXT: [[MIN_ITERS_CHECK:%.*]] = icmp ule i64 [[N]], 4
183189
; CHECK-NEXT: br i1 [[MIN_ITERS_CHECK]], label %[[SCALAR_PH:.*]], label %[[VECTOR_SCEVCHECK:.*]]
184190
; CHECK: [[VECTOR_SCEVCHECK]]:
185-
; CHECK-NEXT: [[TMP0:%.*]] = add i64 [[N]], -17
186-
; CHECK-NEXT: [[TMP1:%.*]] = icmp ult i64 [[TMP0]], -16
191+
; CHECK-NEXT: [[TMP0:%.*]] = add i64 [[N]], -1
192+
; CHECK-NEXT: [[TMP1:%.*]] = icmp ugt i64 [[TMP0]], 15
187193
; CHECK-NEXT: br i1 [[TMP1]], label %[[SCALAR_PH]], label %[[VECTOR_PH:.*]]
188194
; CHECK: [[VECTOR_PH]]:
189-
; CHECK-NEXT: [[N_MOD_VF:%.*]] = and i64 [[N]], 3
195+
; CHECK-NEXT: [[N_MOD_VF:%.*]] = urem i64 [[N]], 4
190196
; CHECK-NEXT: [[TMP2:%.*]] = icmp eq i64 [[N_MOD_VF]], 0
191197
; CHECK-NEXT: [[TMP7:%.*]] = select i1 [[TMP2]], i64 4, i64 [[N_MOD_VF]]
192-
; CHECK-NEXT: [[N_VEC:%.*]] = sub nsw i64 [[N]], [[TMP7]]
198+
; CHECK-NEXT: [[N_VEC:%.*]] = sub i64 [[N]], [[TMP7]]
193199
; CHECK-NEXT: br label %[[VECTOR_BODY:.*]]
194200
; CHECK: [[VECTOR_BODY]]:
195201
; CHECK-NEXT: [[INDEX:%.*]] = phi i64 [ 0, %[[VECTOR_PH]] ], [ [[INDEX_NEXT:%.*]], %[[VECTOR_BODY]] ]
196202
; CHECK-NEXT: [[TMP8:%.*]] = mul nuw nsw i64 [[INDEX]], 3
197-
; CHECK-NEXT: [[TMP3:%.*]] = and i64 [[TMP8]], 12
203+
; CHECK-NEXT: [[TMP3:%.*]] = and i64 [[TMP8]], 15
198204
; CHECK-NEXT: [[TMP4:%.*]] = getelementptr inbounds nuw i32, ptr [[X]], i64 [[TMP3]]
199205
; CHECK-NEXT: [[WIDE_VEC:%.*]] = load <12 x i32>, ptr [[TMP4]], align 4
200206
; CHECK-NEXT: [[STRIDED_VEC:%.*]] = shufflevector <12 x i32> [[WIDE_VEC]], <12 x i32> poison, <4 x i32> <i32 0, i32 3, i32 6, i32 9>
201207
; CHECK-NEXT: [[TMP5:%.*]] = getelementptr inbounds nuw i32, ptr [[OUT]], i64 [[INDEX]]
202-
; CHECK-NEXT: store <4 x i32> [[STRIDED_VEC]], ptr [[TMP5]], align 4
208+
; CHECK-NEXT: [[TMP9:%.*]] = getelementptr inbounds nuw i32, ptr [[TMP5]], i32 0
209+
; CHECK-NEXT: store <4 x i32> [[STRIDED_VEC]], ptr [[TMP9]], align 4
203210
; CHECK-NEXT: [[INDEX_NEXT]] = add nuw i64 [[INDEX]], 4
204211
; CHECK-NEXT: [[TMP6:%.*]] = icmp eq i64 [[INDEX_NEXT]], [[N_VEC]]
205212
; CHECK-NEXT: br i1 [[TMP6]], label %[[MIDDLE_BLOCK:.*]], label %[[VECTOR_BODY]], !llvm.loop [[LOOP6:![0-9]+]]

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