@@ -1545,16 +1545,16 @@ pub unsafe fn vmovq_n_u8(value: u8) -> uint8x16_t {
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#[ cfg_attr( target_arch = "arm" , target_feature( enable = "v7" ) ) ]
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#[ cfg_attr( test, assert_instr( ld1) ) ]
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pub unsafe fn vld1q_s8 ( addr : * const i8 ) -> int8x16_t {
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- * ( addr as * const int8x16_t )
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+ ptr :: read ( addr as * const int8x16_t )
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}
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- /// int8x16_t vld1q_s8 (int8_t const * ptr)
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+ /// int8x16_t vld1q_u8 (uint8_t const * ptr)
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#[ inline]
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#[ target_feature( enable = "neon" ) ]
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#[ cfg_attr( target_arch = "arm" , target_feature( enable = "v7" ) ) ]
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#[ cfg_attr( test, assert_instr( ld1) ) ]
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pub unsafe fn vld1q_u8 ( addr : * const u8 ) -> uint8x16_t {
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- * ( addr as * const uint8x16_t )
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+ ptr :: read ( addr as * const uint8x16_t )
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}
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/// void vst1q_u8 (uint8_t * ptr, uint8x16_t val)
@@ -1602,6 +1602,9 @@ arm_reinterpret!(vreinterpretq_u8_s8, int8x16_t, uint8x16_t);
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#[ cfg_attr( target_arch = "arm" , target_feature( enable = "v7" ) ) ]
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#[ cfg_attr( test, assert_instr( ext) ) ]
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pub unsafe fn vextq_s8 ( a : int8x16_t , b : int8x16_t , n : i32 ) -> int8x16_t {
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+ if n < 0 || n > 16 {
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+ unreachable_unchecked ( ) ;
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+ } ;
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match n {
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0 => b,
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1 => int8x16_t (
@@ -1660,6 +1663,9 @@ pub unsafe fn vextq_s8(a: int8x16_t, b: int8x16_t, n: i32) -> int8x16_t {
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#[ cfg_attr( target_arch = "arm" , target_feature( enable = "v7" ) ) ]
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#[ cfg_attr( test, assert_instr( ushr) ) ]
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pub unsafe fn vshrq_n_u8 ( a : uint8x16_t , n : i32 ) -> uint8x16_t {
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+ if n < 0 || n > 7 {
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+ unreachable_unchecked ( ) ;
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+ } ;
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uint8x16_t (
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a. 0 >> n,
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a. 1 >> n,
@@ -1686,6 +1692,9 @@ pub unsafe fn vshrq_n_u8(a: uint8x16_t, n: i32) -> uint8x16_t {
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#[ cfg_attr( target_arch = "arm" , target_feature( enable = "v7" ) ) ]
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#[ cfg_attr( test, assert_instr( ushl) ) ]
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pub unsafe fn vshlq_n_u8 ( a : uint8x16_t , n : i32 ) -> uint8x16_t {
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+ if n < 0 || n > 7 {
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+ unreachable_unchecked ( ) ;
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+ } ;
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uint8x16_t (
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a. 0 << n,
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a. 1 << n,
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