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lqdAmanieu
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convert _mm_mask_i64gather_pd to const generics
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crates/core_arch/src/x86/avx2.rs

Lines changed: 6 additions & 12 deletions
Original file line numberDiff line numberDiff line change
@@ -1752,24 +1752,19 @@ pub unsafe fn _mm_i64gather_pd<const SCALE: i32>(slice: *const f64, offsets: __m
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/// [Intel's documentation](https://software.intel.com/sites/landingpage/IntrinsicsGuide/#text=_mm_mask_i64gather_pd)
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#[inline]
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#[target_feature(enable = "avx2")]
1755-
#[cfg_attr(test, assert_instr(vgatherqpd, scale = 1))]
1756-
#[rustc_args_required_const(4)]
1755+
#[cfg_attr(test, assert_instr(vgatherqpd, SCALE = 1))]
1756+
#[rustc_legacy_const_generics(4)]
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#[stable(feature = "simd_x86", since = "1.27.0")]
1758-
pub unsafe fn _mm_mask_i64gather_pd(
1758+
pub unsafe fn _mm_mask_i64gather_pd<const SCALE: i32>(
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src: __m128d,
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slice: *const f64,
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offsets: __m128i,
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mask: __m128d,
1763-
scale: i32,
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) -> __m128d {
1764+
static_assert_imm8_scale!(SCALE);
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let slice = slice as *const i8;
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let offsets = offsets.as_i64x2();
1767-
macro_rules! call {
1768-
($imm8:expr) => {
1769-
pgatherqpd(src, slice, offsets, mask, $imm8)
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};
1771-
}
1772-
constify_imm8_gather!(scale, call)
1767+
pgatherqpd(src, slice, offsets, mask, SCALE as i8)
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}
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/// Returns values from `slice` at offsets determined by `offsets * scale`,
@@ -5892,12 +5887,11 @@ mod tests {
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j += 1.0;
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}
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// A multiplier of 8 is word-addressing for f64s
5895-
let r = _mm_mask_i64gather_pd(
5890+
let r = _mm_mask_i64gather_pd::<8>(
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_mm_set1_pd(256.0),
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arr.as_ptr(),
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_mm_setr_epi64x(16, 16),
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_mm_setr_pd(-1.0, 0.0),
5900-
8,
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);
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assert_eq_m128d(r, _mm_setr_pd(16.0, 256.0));
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}

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