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std_detect: Use riscv_hwprobe on RISC-V Linux/Android #1762

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std_detect: Use riscv_hwprobe on RISC-V Linux/Android #1762

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1ece49d
std_detect: Use riscv_hwprobe on RISC-V Linux/Android
taiki-e Mar 31, 2025
507193a
std_detect: Enable cfg check for RISC-V vector-related target features
taiki-e Apr 1, 2025
eeb0002
std_detect: Remove RISC-V privileged features
taiki-e Apr 1, 2025
1474c1d
std_detect: Check hwcap to detect RISC-V V extension
taiki-e Apr 1, 2025
5bee27c
std_detect: Remove comment about zvl*b target features
taiki-e Apr 10, 2025
669e553
std_detect: Enable riscv_linux test also on Android
taiki-e Apr 10, 2025
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5 changes: 4 additions & 1 deletion crates/std_detect/README.md
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Original file line number Diff line number Diff line change
Expand Up @@ -56,11 +56,14 @@ crate from working on applications in which `std` is not available.
[`cupid`](https://crates.io/crates/cupid) crate.

* Linux/Android:
* `arm{32, 64}`, `mips{32,64}{,el}`, `powerpc{32,64}{,le}`, `riscv{32,64}`, `loongarch64`, `s390x`:
* `arm{32, 64}`, `mips{32,64}{,el}`, `powerpc{32,64}{,le}`, `loongarch64`, `s390x`:
`std_detect` supports these on Linux by querying ELF auxiliary vectors (using `getauxval`
when available), and if that fails, by querying `/proc/cpuinfo`.
* `arm64`: partial support for doing run-time feature detection by directly
querying `mrs` is implemented for Linux >= 4.11, but not enabled by default.
* `riscv{32,64}`:
`std_detect` supports these on Linux by querying `riscv_hwprobe`, and
by querying ELF auxiliary vectors (using `getauxval` when available).

* FreeBSD:
* `arm32`, `powerpc64`: `std_detect` supports these on FreeBSD by querying ELF
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81 changes: 58 additions & 23 deletions crates/std_detect/src/detect/arch/riscv.rs
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Expand Up @@ -79,14 +79,6 @@ features! {
/// * P: `"p"`
/// * Zam: `"zam"`
///
/// Defined by Privileged Specification:
///
/// * Supervisor: `"s"`
/// * Svnapot: `"svnapot"`
/// * Svpbmt: `"svpbmt"`
/// * Svinval: `"svinval"`
/// * Hypervisor: `"h"`
///
/// [ISA manual]: https://github.com/riscv/riscv-isa-manual/
#[stable(feature = "riscv_ratified", since = "1.78.0")]

Expand Down Expand Up @@ -125,6 +117,10 @@ features! {

@FEATURE: #[stable(feature = "riscv_ratified", since = "1.78.0")] a: "a";
/// "A" Extension for Atomic Instructions
@FEATURE: #[unstable(feature = "stdarch_riscv_feature_detection", issue = "111192")] zacas: "zacas";
/// Atomic Compare-And-Swap Instructions
@FEATURE: #[unstable(feature = "stdarch_riscv_feature_detection", issue = "111192")] zawrs: "zawrs";
/// Wait on Reservation Set
@FEATURE: #[unstable(feature = "stdarch_riscv_feature_detection", issue = "111192")] zam: "zam";
without cfg check: true;
/// "Zam" Extension for Misaligned Atomics
Expand Down Expand Up @@ -194,23 +190,62 @@ features! {

@FEATURE: #[unstable(feature = "stdarch_riscv_feature_detection", issue = "111192")] v: "v";
/// "V" Extension for Vector Operations
@FEATURE: #[unstable(feature = "stdarch_riscv_feature_detection", issue = "111192")] zvfh: "zvfh";
/// Vector Extension for Half-Precision Floating-Point
@FEATURE: #[unstable(feature = "stdarch_riscv_feature_detection", issue = "111192")] zvfhmin: "zvfhmin";
/// Vector Extension for Minimal Half-Precision Floating-Point
@FEATURE: #[unstable(feature = "stdarch_riscv_feature_detection", issue = "111192")] zve32x: "zve32x";
/// Vector Extensions for Embedded Processors
@FEATURE: #[unstable(feature = "stdarch_riscv_feature_detection", issue = "111192")] zve32f: "zve32f";
/// Vector Extensions for Embedded Processors
@FEATURE: #[unstable(feature = "stdarch_riscv_feature_detection", issue = "111192")] zve64x: "zve64x";
/// Vector Extensions for Embedded Processors
@FEATURE: #[unstable(feature = "stdarch_riscv_feature_detection", issue = "111192")] zve64f: "zve64f";
/// Vector Extensions for Embedded Processors
@FEATURE: #[unstable(feature = "stdarch_riscv_feature_detection", issue = "111192")] zve64d: "zve64d";
/// Vector Extensions for Embedded Processors

@FEATURE: #[unstable(feature = "stdarch_riscv_feature_detection", issue = "111192")] svnapot: "svnapot";
without cfg check: true;
/// "Svnapot" Extension for NAPOT Translation Contiguity
@FEATURE: #[unstable(feature = "stdarch_riscv_feature_detection", issue = "111192")] svpbmt: "svpbmt";
without cfg check: true;
/// "Svpbmt" Extension for Page-Based Memory Types
@FEATURE: #[unstable(feature = "stdarch_riscv_feature_detection", issue = "111192")] svinval: "svinval";
without cfg check: true;
/// "Svinval" Extension for Fine-Grained Address-Translation Cache Invalidation
@FEATURE: #[unstable(feature = "stdarch_riscv_feature_detection", issue = "111192")] h: "h";
without cfg check: true;
/// "H" Extension for Hypervisor Support
// FIXME: we can implement this by getting the current vlen
// zvl*b: Minimum Vector Length Standard Extensions
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@a4lg a4lg Apr 3, 2025

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Despite that I can allow this comment alone (so that you can keep up with this PR), I disagree (actually) adding all Zvl*b extensions (in total of 12; * being a power of two between 32 and 65536 inclusive) for being too redundant (e.g. 256 implies 128, 128 implies 64 and so on) and either:

  • Unlikely to be referred by real-world programs (due to the software-side nature of RVV) or
  • Likely that (for specialized programs) just knowing the vector length is not enough (it is said that implementing RVV to the hardware is harder than implementing regular SIMD instructions and some reports suggested that the actual performance boost heavily depends on the actual vector engine implementation) so that adding Zvl*b alone will not help them much.

I acknowledge that there's still a need to retrieve the vector register size and I think an intrinsic (which returns the vector register size) would be a better solution.

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@taiki-e taiki-e Apr 10, 2025

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It indeed makes more sense to have it as a core::arch intrinsic, since nothing OS-specific is needed to get the VLEN, and the actual length information can be obtained in a single call.

Removed that code comment.


@FEATURE: #[unstable(feature = "stdarch_riscv_feature_detection", issue = "111192")] zvkb: "zvkb";
/// Vector Bit-manipulation used in Cryptography
@FEATURE: #[unstable(feature = "stdarch_riscv_feature_detection", issue = "111192")] zvbb: "zvbb";
/// Vector basic bit-manipulation instructions
@FEATURE: #[unstable(feature = "stdarch_riscv_feature_detection", issue = "111192")] zvbc: "zvbc";
/// Vector Carryless Multiplication
@FEATURE: #[unstable(feature = "stdarch_riscv_feature_detection", issue = "111192")] zvkg: "zvkg";
/// Vector GCM instructions for Cryptography
@FEATURE: #[unstable(feature = "stdarch_riscv_feature_detection", issue = "111192")] zvkned: "zvkned";
/// Vector AES Encryption & Decryption (Single Round)
@FEATURE: #[unstable(feature = "stdarch_riscv_feature_detection", issue = "111192")] zvknha: "zvknha";
/// Vector SHA-2 (SHA-256 only))
@FEATURE: #[unstable(feature = "stdarch_riscv_feature_detection", issue = "111192")] zvknhb: "zvknhb";
/// Vector SHA-2 (SHA-256 and SHA-512)
@FEATURE: #[unstable(feature = "stdarch_riscv_feature_detection", issue = "111192")] zvksed: "zvksed";
/// SM4 Block Cipher Instructions
@FEATURE: #[unstable(feature = "stdarch_riscv_feature_detection", issue = "111192")] zvksh: "zvksh";
/// SM3 Hash Function Instructions
@FEATURE: #[unstable(feature = "stdarch_riscv_feature_detection", issue = "111192")] zvkn: "zvkn";
/// Shorthand for 'Zvkned', 'Zvknhb', 'Zvkb', and 'Zvkt'
@FEATURE: #[unstable(feature = "stdarch_riscv_feature_detection", issue = "111192")] zvknc: "zvknc";
/// Shorthand for 'Zvkn' and 'Zvbc'
@FEATURE: #[unstable(feature = "stdarch_riscv_feature_detection", issue = "111192")] zvkng: "zvkng";
/// Shorthand for 'Zvkn' and 'Zvkg'
@FEATURE: #[unstable(feature = "stdarch_riscv_feature_detection", issue = "111192")] zvks: "zvks";
/// Shorthand for 'Zvksed', 'Zvksh', 'Zvkb', and 'Zvkt'
@FEATURE: #[unstable(feature = "stdarch_riscv_feature_detection", issue = "111192")] zvksc: "zvksc";
/// Shorthand for 'Zvks' and 'Zvbc'
@FEATURE: #[unstable(feature = "stdarch_riscv_feature_detection", issue = "111192")] zvksg: "zvksg";
/// Shorthand for 'Zvks' and 'Zvkg'
@FEATURE: #[unstable(feature = "stdarch_riscv_feature_detection", issue = "111192")] zvkt: "zvkt";
/// Vector Data-Independent Execution Latency

@FEATURE: #[unstable(feature = "stdarch_riscv_feature_detection", issue = "111192")] unaligned_scalar_mem: "unaligned-scalar-mem";
/// Has reasonably performant unaligned scalar
@FEATURE: #[unstable(feature = "stdarch_riscv_feature_detection", issue = "111192")] unaligned_vector_mem: "unaligned-vector-mem";
/// Has reasonably performant unaligned vector

@FEATURE: #[unstable(feature = "stdarch_riscv_feature_detection", issue = "111192")] s: "s";
without cfg check: true;
/// Supervisor-Level ISA
@FEATURE: #[unstable(feature = "stdarch_riscv_feature_detection", issue = "111192")] j: "j";
without cfg check: true;
/// "J" Extension for Dynamically Translated Languages
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