build: Bump zerocopy to 0.8.23

Cargo.toml

@@ -10,4 +10,4 @@ license = "Apache-2.0"
 edition = "2021"
 
 [dependencies]
-zerocopy = { version = "0.7.1", features = ["derive"] }
+zerocopy = { version = "0.8.23", features = ["derive"] }

src/bert.rs

@@ -3,7 +3,10 @@
 // SPDX-License-Identifier: Apache-2.0
 //
 
-use zerocopy::{byteorder, byteorder::LE, AsBytes};
+use zerocopy::{
+    byteorder::{self, LE},
+    Immutable, IntoBytes,
+};
 
 extern crate alloc;
 
@@ -17,7 +20,7 @@ type U64 = byteorder::U64<LE>;
 /// unhandled errors that occurred in the previous boot. The format of
 /// the Boot Error Region follows that of an `Error Status Block`.
 #[repr(C, packed)]
-#[derive(Clone, Copy, Debug, Default, AsBytes)]
+#[derive(Clone, Copy, Debug, Default, IntoBytes, Immutable)]
 pub struct BERT {
     header: TableHeader,
     error_region_length: U32,

src/cedt.rs

@@ -3,7 +3,7 @@
 // SPDX-License-Identifier: Apache-2.0
 //
 
-use zerocopy::AsBytes;
+use zerocopy::IntoBytes;
 
 extern crate alloc;
 use alloc::{boxed::Box, vec::Vec};

src/facs.rs

@@ -4,13 +4,16 @@
 //
 
 use crate::{Aml, AmlSink};
-use zerocopy::{byteorder, byteorder::LE, AsBytes};
+use zerocopy::{
+    byteorder::{self, LE},
+    Immutable, IntoBytes,
+};
 
 type U32 = byteorder::U32<LE>;
 type U64 = byteorder::U64<LE>;
 
 #[repr(C, packed)]
-#[derive(Clone, Copy, Default, AsBytes)]
+#[derive(Clone, Copy, Default, IntoBytes, Immutable)]
 pub struct FACS {
     pub signature: [u8; 4],
     pub length: U32,

src/fadt.rs

@@ -4,7 +4,7 @@
 //
 
 use crate::{gas::GAS, Aml, AmlSink};
-use zerocopy::{byteorder, byteorder::LE, AsBytes};
+use zerocopy::{byteorder, byteorder::LE, Immutable, IntoBytes};
 
 type U16 = byteorder::U16<LE>;
 type U32 = byteorder::U32<LE>;
@@ -64,7 +64,7 @@ pub enum PmProfile {
 }
 
 #[repr(C, packed)]
-#[derive(Clone, Copy, Default, AsBytes)]
+#[derive(Clone, Copy, Default, IntoBytes, Immutable)]
 pub struct FADTBuilder {
     pub signature: [u8; 4],
     pub length: U32,

src/gas.rs

@@ -4,12 +4,12 @@
 //
 
 use crate::{Aml, AmlSink};
-use zerocopy::{byteorder, byteorder::LE, AsBytes};
+use zerocopy::{byteorder, byteorder::LE, Immutable, IntoBytes};
 
 type U64 = byteorder::U64<LE>;
 
 #[repr(u8)]
-#[derive(Clone, Copy, Debug, AsBytes, Default)]
+#[derive(Clone, Copy, Debug, IntoBytes, Default, Immutable)]
 pub enum AddressSpace {
     #[default]
     SystemMemory = 0x0,
@@ -28,7 +28,7 @@ pub enum AddressSpace {
 }
 
 #[repr(u8)]
-#[derive(Clone, Copy, Debug, AsBytes, Default)]
+#[derive(Clone, Copy, Debug, IntoBytes, Default, Immutable)]
 pub enum AccessSize {
     #[default]
     Undefined = 0,
@@ -39,7 +39,7 @@ pub enum AccessSize {
 }
 
 #[repr(C, packed)]
-#[derive(Clone, Copy, Debug, AsBytes, Default)]
+#[derive(Clone, Copy, Debug, IntoBytes, Default, Immutable)]
 pub struct GAS {
     pub address_space_id: AddressSpace,
     pub register_bit_width: u8,

src/hest.rs

@@ -3,7 +3,10 @@
 // SPDX-License-Identifier: Apache-2.0
 //
 
-use zerocopy::{byteorder, byteorder::LE, AsBytes};
+use zerocopy::{
+    byteorder::{self, LE},
+    Immutable, IntoBytes,
+};
 
 extern crate alloc;
 use alloc::{boxed::Box, vec::Vec};
@@ -74,7 +77,7 @@ impl HEST {
 
     pub fn add_structure<T>(&mut self, t: T)
     where
-        T: Aml + AsBytes + Clone + 'static,
+        T: Aml + IntoBytes + Immutable + Clone + 'static,
     {
         self.update_header(t.as_bytes());
         self.structures.push(Box::new(t));
@@ -97,7 +100,7 @@ impl Aml for HEST {
 /// This structure contains information for configuring AER support on
 /// a given root port.
 #[repr(C, packed)]
-#[derive(Clone, Copy, Debug, Default, AsBytes)]
+#[derive(Clone, Copy, Debug, Default, IntoBytes, Immutable)]
 pub struct PcieAerRootPort {
     r#type: U16,
     source_id: U16,
@@ -189,7 +192,7 @@ aml_as_bytes!(PcieAerRootPort);
 /// otherwise there should be one entry for each device that supports
 /// AER.
 #[repr(C, packed)]
-#[derive(Clone, Copy, Debug, Default, AsBytes)]
+#[derive(Clone, Copy, Debug, Default, IntoBytes, Immutable)]
 pub struct PcieAerDevice {
     r#type: U16,
     source_id: U16,
@@ -250,7 +253,7 @@ aml_as_bytes!(PcieAerDevice);
 /// PCIe/PCI-X bridges that support AER implement fields that control
 /// the behavior of how errors are reported across the bridge.
 #[repr(C, packed)]
-#[derive(Clone, Copy, Debug, Default, AsBytes)]
+#[derive(Clone, Copy, Debug, Default, IntoBytes, Immutable)]
 pub struct PcieAerBridge {
     r#type: U16,
     source_id: U16,
@@ -321,7 +324,7 @@ aml_as_bytes!(PcieAerBridge);
 /// for configure and control operations, therefore the error source
 /// must be configured by firmware during boot.
 #[repr(C, packed)]
-#[derive(Clone, Copy, Debug, Default, AsBytes)]
+#[derive(Clone, Copy, Debug, Default, IntoBytes, Immutable)]
 pub struct GenericHardwareSource {
     r#type: U16,
     source_id: U16,
@@ -366,7 +369,7 @@ impl GenericHardwareSource {
 aml_as_bytes!(GenericHardwareSource);
 
 #[repr(C, packed)]
-#[derive(Clone, Copy, Debug, Default, AsBytes)]
+#[derive(Clone, Copy, Debug, Default, IntoBytes, Immutable)]
 pub struct NotificationStructure {
     r#type: NotificationType,
     length: u8,
@@ -400,7 +403,7 @@ impl NotificationStructure {
 aml_as_bytes!(NotificationStructure);
 
 #[repr(u8)]
-#[derive(Clone, Copy, Debug, Default, AsBytes)]
+#[derive(Clone, Copy, Debug, Default, IntoBytes, Immutable)]
 pub enum NotificationType {
     #[default]
     Polled = 0,
@@ -422,7 +425,7 @@ pub enum NotificationType {
 }
 
 #[repr(u32)]
-#[derive(Copy, Clone, Debug, AsBytes, Default)]
+#[derive(Copy, Clone, Debug, IntoBytes, Immutable, Default)]
 pub enum ErrorSeverity {
     Recoverable = 0,
     Fatal = 1,
@@ -543,7 +546,7 @@ impl Aml for GenericErrorData {
 /// for HW-reduced platforms that rely on "RAS controllers" to generate generic
 /// error records.
 #[repr(C, packed)]
-#[derive(Clone, Copy, Debug, Default, AsBytes)]
+#[derive(Clone, Copy, Debug, Default, IntoBytes, Immutable)]
 pub struct GenericHardwareSourceV2 {
     r#type: U16,
     source_id: U16,

src/hmat.rs

@@ -3,7 +3,10 @@
 // SPDX-License-Identifier: Apache-2.0
 //
 
-use zerocopy::{byteorder, byteorder::LE, AsBytes};
+use zerocopy::{
+    byteorder::{self, LE},
+    Immutable, IntoBytes,
+};
 
 extern crate alloc;
 use alloc::{boxed::Box, vec, vec::Vec};
@@ -101,7 +104,7 @@ impl Aml for HMAT {
 // by the memory subsystem and its associativity with a processor
 // proximity domain.
 #[repr(C, packed)]
-#[derive(Clone, Copy, Debug, Default, AsBytes)]
+#[derive(Clone, Copy, Debug, Default, IntoBytes, Immutable)]
 pub struct MemoryProximityDomain {
     r#type: U16,
     _reserved0: U16,

src/lib.rs

@@ -34,7 +34,10 @@ pub mod xsdt;
 
 extern crate alloc;
 
-use zerocopy::{byteorder, byteorder::LE, AsBytes};
+use zerocopy::{
+    byteorder::{self, LE},
+    Immutable, IntoBytes,
+};
 
 type U32 = byteorder::U32<LE>;
 
@@ -89,7 +92,7 @@ impl AmlSink for alloc::vec::Vec<u8> {
 
 /// Standard header for many ACPI tables
 #[repr(C, packed)]
-#[derive(Clone, Copy, Debug, Default, AsBytes)]
+#[derive(Clone, Copy, Debug, Default, IntoBytes, Immutable)]
 struct TableHeader {
     pub signature: [u8; 4],
     pub length: U32,

src/madt.rs

@@ -3,7 +3,10 @@
 // SPDX-License-Identifier: Apache-2.0
 //
 
-use zerocopy::{byteorder, byteorder::LE, AsBytes};
+use zerocopy::{
+    byteorder::{self, LE},
+    Immutable, IntoBytes,
+};
 
 extern crate alloc;
 use alloc::{boxed::Box, vec::Vec};
@@ -30,7 +33,7 @@ enum MadtStructureType {
 }
 
 #[repr(C, packed)]
-#[derive(Clone, Copy, Debug, Default, AsBytes)]
+#[derive(Clone, Copy, Debug, Default, IntoBytes, Immutable)]
 struct Header {
     table_header: TableHeader,
     /// Must be ignored by OSPM for RISC-V
@@ -111,7 +114,7 @@ impl MADT {
 
     pub fn add_structure<T>(&mut self, t: T)
     where
-        T: Aml + AsBytes + Clone + 'static,
+        T: Aml + IntoBytes + Immutable + Clone + 'static,
     {
         self.update_header(t.as_bytes());
         self.structures.push(Box::new(t));
@@ -136,7 +139,7 @@ impl Aml for MADT {
 
 /// Processor-Local APIC
 #[repr(C, packed)]
-#[derive(Clone, Copy, Debug, Default, AsBytes)]
+#[derive(Clone, Copy, Debug, Default, IntoBytes, Immutable)]
 pub struct ProcessorLocalApic {
     r#type: u8,
     length: u8,
@@ -169,7 +172,7 @@ aml_as_bytes!(ProcessorLocalApic);
 
 /// I/O APIC
 #[repr(C, packed)]
-#[derive(Clone, Copy, Debug, Default, AsBytes)]
+#[derive(Clone, Copy, Debug, Default, IntoBytes, Immutable)]
 pub struct IoApic {
     r#type: u8,
     length: u8,
@@ -196,7 +199,7 @@ aml_as_bytes!(IoApic);
 
 /// GIC CPU Interface (GICC)
 #[repr(C, packed)]
-#[derive(Clone, Copy, Debug, Default, AsBytes)]
+#[derive(Clone, Copy, Debug, Default, IntoBytes, Immutable)]
 pub struct Gicc {
     r#type: u8,
     length: u8,
@@ -302,7 +305,7 @@ pub enum GicVersion {
 
 /// GIC Distributor (GICD) Structure
 #[repr(C, packed)]
-#[derive(Clone, Copy, Debug, Default, AsBytes)]
+#[derive(Clone, Copy, Debug, Default, IntoBytes, Immutable)]
 pub struct Gicd {
     r#type: u8,
     length: u8,
@@ -334,7 +337,7 @@ aml_as_bytes!(Gicd);
 
 /// GIC MSI Frame Structure
 #[repr(C, packed)]
-#[derive(Clone, Copy, Debug, Default, AsBytes)]
+#[derive(Clone, Copy, Debug, Default, IntoBytes, Immutable)]
 pub struct GicMsi {
     r#type: u8,
     length: u8,
@@ -372,7 +375,7 @@ aml_as_bytes!(GicMsi);
 
 /// GIC Redistributor (GICR) Structure
 #[repr(C, packed)]
-#[derive(Clone, Copy, Debug, Default, AsBytes)]
+#[derive(Clone, Copy, Debug, Default, IntoBytes, Immutable)]
 pub struct Gicr {
     r#type: u8,
     length: u8,
@@ -398,7 +401,7 @@ aml_as_bytes!(Gicr);
 
 /// GIC Interrupt Translation Service (ITS) Structure
 #[repr(C, packed)]
-#[derive(Clone, Copy, Debug, Default, AsBytes)]
+#[derive(Clone, Copy, Debug, Default, IntoBytes, Immutable)]
 pub struct GicIts {
     r#type: u8,
     length: u8,
@@ -428,7 +431,7 @@ aml_as_bytes!(GicIts);
 /// RISC-V platforms need to have a simple, per-hart interrupt controller
 /// available to supervisor mode.
 #[repr(C, packed)]
-#[derive(Clone, Copy, Debug, Default, AsBytes)]
+#[derive(Clone, Copy, Debug, Default, IntoBytes, Immutable)]
 pub struct RINTC {
     r#type: u8,
     length: u8,
@@ -486,7 +489,7 @@ aml_as_bytes!(RINTC);
 // provides information common across processors. The per-processor
 // information will be provided by the RINTC structure.
 #[repr(C, packed)]
-#[derive(Copy, Clone, Debug, Default, AsBytes)]
+#[derive(Copy, Clone, Debug, Default, IntoBytes, Immutable)]
 pub struct IMSIC {
     r#type: u8,
     length: u8,
@@ -547,7 +550,7 @@ aml_as_bytes!(IMSIC);
 // interrupts only in the form of MSIs. In that case, the role of an
 // APLIC is to convert wired interrupts into MSIs for harts.
 #[repr(C, packed)]
-#[derive(Copy, Clone, Debug, AsBytes)]
+#[derive(Copy, Clone, Debug, IntoBytes, Immutable)]
 pub struct APLIC {
     r#type: u8,
     length: u8,
@@ -596,7 +599,7 @@ assert_same_size!(APLIC, [u8; 36]);
 aml_as_bytes!(APLIC);
 
 #[repr(C, packed)]
-#[derive(Copy, Clone, Debug, AsBytes)]
+#[derive(Copy, Clone, Debug, IntoBytes, Immutable)]
 pub struct PLIC {
     r#type: u8,
     length: u8,

src/mcfg.rs

@@ -7,7 +7,10 @@ extern crate alloc;
 
 use crate::{Aml, AmlSink, Checksum, TableHeader};
 use alloc::vec::Vec;
-use zerocopy::{byteorder, byteorder::LE, AsBytes};
+use zerocopy::{
+    byteorder::{self, LE},
+    Immutable, IntoBytes,
+};
 
 type U16 = byteorder::U16<LE>;
 type U64 = byteorder::U64<LE>;
@@ -85,7 +88,7 @@ impl Aml for MCFG {
 }
 
 #[repr(C, packed)]
-#[derive(Copy, Clone, Debug, Default, AsBytes)]
+#[derive(Copy, Clone, Debug, Default, IntoBytes, Immutable)]
 struct EcamEntry {
     base_addr: U64,
     segment: U16,