WIP: Xen crates redesign and oxerun revamp oriented around PVH

Cargo.toml

@@ -4,6 +4,7 @@ members = [
     "xen",
     "xen-bindings",
     "xen-ioctls",
+    "xen-unix",
     "xen-store",
     "xen-sys",
 ]

oxerun/aarch64-xen-hvm.json → aarch64-xen-hvm.json

@@ -1,6 +1,6 @@
 {
   "arch": "aarch64",
-  "data-layout": "e-m:e-i8:8:32-i16:16:32-i64:64-i128:128-n32:64-S128-Fn32",
+  "data-layout": "e-m:e-p270:32:32-p271:32:32-p272:64:64-i8:8:32-i16:16:32-i64:64-i128:128-n32:64-S128-Fn32",
   "disable-redzone": true,
   "executables": true,
   "features": "+strict-align,+neon,+fp-armv8",
@@ -13,6 +13,6 @@
   "max-atomic-width": 128,
   "panic-strategy": "abort",
   "relocation-model": "static",
-  "target-pointer-width": "64",
+  "target-pointer-width": 64,
   "vendor": "xen"
 }

oxerun/Cargo.toml

@@ -1,14 +1,51 @@
 [package]
-authors = ["Doug Goldstein <cardoe@cardoe.com>"]
+authors = [
+    "Doug Goldstein <cardoe@cardoe.com>",
+    "Teddy Astie <teddy.astie@vates.tech>",
+    "The Rust Hypervisor Firmware Authors", # Based on Rust Hypervisor Firmware code
+]
 description = "Compiler bits to create Rust unikernels for Xen"
 homepage = "https://github.com/rust-vmm/xen-sys"
 repository = "https://github.com/rust-vmm/xen-sys.git"
-license = "Apache-2.0 OR MIT"
+license = "Apache-2.0"
 name = "oxerun"
 readme = "README.md"
 version = "0.1.0"
-edition = "2018"
+edition = "2024"
+
+[profile.dev]
+panic = "abort"
+
+[profile.release]
+panic = "abort"
+lto = "fat"
 
 [dependencies]
+bitflags = "2.9.1"
+atomic_refcell = "0.1.13"
+log = "0.4.27"
+volatile = { version = "0.6.1", features = ["derive", "unstable"] }
 xen = { path = "../xen" }
 xen-sys = { path = "../xen-sys" }
+enum_dispatch = "0.3.13"
+
+[target.'cfg(target_arch = "aarch64")'.dependencies]
+tock-registers = "0.10.0"
+aarch64-cpu = "10.0.0"
+fdt = "0.1.5"
+
+[target.'cfg(target_arch = "x86_64")'.dependencies]
+uart_16550 = "0.4.0"
+x86_64 = { version = "0.15.2", default-features = false, features = [
+    "instructions",
+] }
+
+[target.'cfg(target_arch = "riscv64")'.dependencies]
+fdt = "0.1.5"
+
+[features]
+sev = ["small_mm"]
+fastabi = []
+
+# Use a small memory model, disable to use a flat 4GB memory model
+small_mm = []

oxerun/README.md

@@ -4,16 +4,20 @@
 
 This is an example build of Rust building a full unikernel for Xen.
 
+You need to use nightly Rust compiler.
+
 ## Building for x86_64:
 
+Using Rust 1.92 nightly build.
+
 ```shell
-# cargo build --target x86_64-xen-pv.json -Zbuild-std=core -Zbuild-std-features=compiler-builtins-mem
+# cargo build -p oxerun -Zbuild-std=core -Zbuild-std-features=compiler-builtins-mem -Zjson-target-spec --target x86_64-xen-hvm.json --bin hello
 ```
 
 And to generate assember files in target/x86_64-xen-pv/{release|debug}/deps/
 
 ```shell
-# RUSTFLAGS="--emit asm -C llvm-args=-x86-asm-syntax=intel" cargo build --target x86_64-xen-pv.json -Zbuild-std=core -Zbuild-std-features=compiler-builtins-mem
+# RUSTFLAGS="--emit asm -C llvm-args=-x86-asm-syntax=intel" cargo build -p oxerun -Zbuild-std=core -Zbuild-std-features=compiler-builtins-mem -Zjson-target-spec --target x86_64-xen-hvm.json --bin hello
 ```
 
 ## Building for aarch64:

oxerun/src/arch/aarch64/asm.rs

@@ -0,0 +1,8 @@
+// SPDX-License-Identifier: Apache-2.0
+// Copyright (C) 2022 Akira Moroo
+
+use super::layout::map;
+use core::arch::global_asm;
+
+global_asm!(include_str!("ram64.s"),
+    FDT_START = const map::dram::FDT_START);

oxerun/src/arch/aarch64/layout.rs

@@ -0,0 +1,129 @@
+// SPDX-License-Identifier: Apache-2.0
+// Copyright (C) 2022 Akira Moroo
+// Copyright (c) 2021-2022 Andre Richter <andre.o.richter@gmail.com>
+
+use core::{
+    cell::UnsafeCell,
+    ops::{Range, RangeInclusive},
+};
+
+use crate::layout::{MemoryAttribute, MemoryDescriptor, MemoryLayout};
+
+use super::paging::*;
+
+unsafe extern "Rust" {
+    unsafe static code_start: UnsafeCell<()>;
+    unsafe static code_end: UnsafeCell<()>;
+    unsafe static data_start: UnsafeCell<()>;
+    unsafe static data_end: UnsafeCell<()>;
+    unsafe static stack_start: UnsafeCell<()>;
+    unsafe static stack_end: UnsafeCell<()>;
+}
+
+pub mod map {
+    // Create page table for 2T
+    pub const END: usize = 0x20_000_000_000;
+
+    // Firmware region won't be used by this firmware, so merge it into mmio region
+    // is harmless and better for management.
+    pub mod mmio {
+        pub const START: usize = 0x0000_0000;
+        pub const PL011_START: usize = 0x0900_0000;
+        pub const PL031_START: usize = 0x0901_0000;
+        pub const END: usize = 0x4000_0000;
+    }
+
+    pub mod dram {
+        pub const FDT_SIZE: usize = 0x0020_0000;
+        pub const ACPI_SIZE: usize = 0x0020_0000;
+
+        pub const START: usize = super::mmio::END;
+        pub const FDT_START: usize = START;
+        pub const ACPI_START: usize = FDT_START + FDT_SIZE;
+        pub const END: usize = super::END;
+    }
+}
+
+pub type KernelAddrSpace = AddressSpace<{ map::END }>;
+
+const NUM_MEM_RANGES: usize = 2;
+
+pub static LAYOUT: KernelVirtualLayout<NUM_MEM_RANGES> = KernelVirtualLayout::new(
+    map::END - 1,
+    [
+        TranslationDescriptor {
+            name: "Device MMIO",
+            virtual_range: RangeInclusive::new(map::mmio::START, map::mmio::END - 1),
+            physical_range_translation: Translation::Identity,
+            attribute_fields: AttributeFields {
+                mem_attributes: MemAttributes::Device,
+                acc_perms: AccessPermissions::ReadWrite,
+                execute_never: true,
+            },
+        },
+        TranslationDescriptor {
+            name: "System Memory",
+            virtual_range: RangeInclusive::new(map::dram::START, map::dram::END - 1),
+            physical_range_translation: Translation::Identity,
+            attribute_fields: AttributeFields {
+                mem_attributes: MemAttributes::CacheableDRAM,
+                acc_perms: AccessPermissions::ReadWrite, // FIXME
+                execute_never: false,
+            },
+        },
+    ],
+);
+
+pub fn virt_mem_layout() -> &'static KernelVirtualLayout<NUM_MEM_RANGES> {
+    &LAYOUT
+}
+
+pub fn mmio_range() -> Range<usize> {
+    map::mmio::START..map::mmio::END
+}
+
+pub fn reserved_range() -> Range<usize> {
+    map::dram::START..map::dram::END
+}
+
+pub fn code_range() -> Range<usize> {
+    unsafe { (code_start.get() as _)..(code_end.get() as _) }
+}
+
+pub fn data_range() -> Range<usize> {
+    unsafe { (data_start.get() as _)..(data_end.get() as _) }
+}
+
+pub fn stack_range() -> Range<usize> {
+    unsafe { (stack_start.get() as _)..(stack_end.get() as _) }
+}
+
+const NUM_MEM_DESCS: usize = 5;
+
+pub static MEM_LAYOUT: MemoryLayout<NUM_MEM_DESCS> = [
+    MemoryDescriptor {
+        name: "MMIO",
+        range: mmio_range,
+        attribute: MemoryAttribute::Mmio,
+    },
+    MemoryDescriptor {
+        name: "Reserved",
+        range: reserved_range,
+        attribute: MemoryAttribute::Unusable,
+    },
+    MemoryDescriptor {
+        name: "Code",
+        range: code_range,
+        attribute: MemoryAttribute::Code,
+    },
+    MemoryDescriptor {
+        name: "Data",
+        range: data_range,
+        attribute: MemoryAttribute::Data,
+    },
+    MemoryDescriptor {
+        name: "Stack",
+        range: stack_range,
+        attribute: MemoryAttribute::Data,
+    },
+];

oxerun/src/arch/aarch64/mod.rs

@@ -0,0 +1,9 @@
+// SPDX-License-Identifier: Apache-2.0
+// Copyright (C) 2022 Akira Moroo
+
+#[cfg(not(test))]
+pub mod asm;
+pub mod layout;
+pub mod paging;
+pub mod simd;
+mod translation;