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Machine Architecture
The processor executes commands read from memory based on the IP register. Most computational commands read data from general-purpose registers (GPR) and write to other GPRs, never overwriting a register unless explicitly specified. Service commands manipulate hidden registers. After execution of the command IP increments by 4 (32-bits). Between two commands an interrupt can occur. In this case, the IP is set to interrupt the handler address.
The are 8 general purpose registers, each holding a 32-bit value. In assembly GPRs are designated as a to h.
Instruction Pointer (IP) in a 32-bit value holding an address of the next command to execute.
Stack Pointer (SP) is a 32-bit value holding the address of the stack head for push/pop operations.
Interrupt Inhibit (II) is a flag set when interrupts should be disabled.
Commands are encoded in memory with opcodes and operand descriptors, each of these values represented by a 32-bit integer.
The commands can be grouped into:
- Move commands:
ldc, mmr, mrm, mrr - Stack commands:
lsp, ssp, push, pop - Control flow commands:
jmp, jgt, cll, ret, hlt - Interrupt control commands:
out, irx, opn, cls - Arithmetic:
add, sub, mul, div, mod, rsh, lsh, bor, xor, band - Protected mode:
spm, lpm - Special commands:
nop - External debug commands:
cpt, aeq
See Machine-Opcodes for reference.
Memory is represented as plain bytearray. An address in memory is in bytes, but any operation manipulates 32-bit (4-byte) values.
The memory layout is as follows:
- Interrupt vector at address INT_VECT_BASE. Size as number of peripheral lines (default 16) multiplied by 4. Each 32-bit element of the vector holds an address of the handler.
- Serial device 'mapped memory' for interaction with the emulated serial device (one word at SERIAL_MM_BASE)
- Read-only-memory (ROM base address)
ROM is emulated by a binary file on the host filesystem, which is passed to the emulator as a parameter. Binary ROM is created by the assembler.
A peripheral emulates input/output devices external to a processor.
A line is a virtual connection point for peripheral devices. It passed signals from a processor to a device and from a device to a processor.
A signal from a device causes an interrupt procedure execution. If interrupts are disabled, a procedure is postponed and will happen as soon as interrupts are enabled again. A unique handler is associated with a line. Its address should be written by start-up code into the interrupt vector. Note that the SEMU machine starts with interrupts being disabled.
A signal to a device is handled differently, depending on the device. Use out command to issue a signal.
There is a fixed number of peripheral/interrupt lines (16 by default).
When a peripheral issues a signal and interrupts are enabled, the following procedure is performed by SEMU:
- Interrupts are disabled
- IP is pushed to the stack
- GPRs are pushed to the stack (a-h)
- Interrupt handler address is calculated based on interrupt vector base address and line number
- IP is set to that address, causing further execution of the handler
A proper handler would perform some quick operation and then return using irx command. Handler may also use lsp command to change the current stack. The most notable usage is context switching based on timer signal.
An interrupt handler number 0 is assigned to 'loopback' devices. This device doesn't support out signals. An interrupt from this device can be triggered programmatically by int command.
More reading: Peripherals
Protected mode engages two features:
- Protected commands are disabled
- MMU is activated
Protected mode is activated by spm command.
Protected commands include out, opn, cls and the spm command itself. Execution of protected command in protected mode initiates an interrupt on VIOLATION_LINE. Violation status can be retrieved by lpm command.
Protected mode disables by calling int command. A handler should be trusted (typically kernel service). Thus code in protected mode it not able to perform any input/output directly and can not hinder preemption.
The memory management unit is activated in protected mode. An attempt to access a memory address outside a protected region will initiate an interrupt on VIOLATION_LINE.
- Bad operand violations
- Protected mode violations
The machine start-up procedure is as follows:
- Each peripheral is started
- GPRs are initialized to 0x00
- IP is set to the ROM base address
- II is set to 'inhibit'
- SP is set to 0x00
- Memory is zeroed
- Protected mode is disabled
- ROM image is copied to memory starting from ROM base address
Memory size and layout may be configured via hwconf.py source file. See Emulator