refactor opcode circuit dispatching and vector allocation

[hero78119]

This is preparation of #1220 to support single circuit subscribe to multi riscv opcodes

Change summary

• Reworked opcode dispatch to use reusable record buffers instead of empty vector per shard. Introduce new dispatcher with circuit registration and error check.
• simplify emulator emit steps -> single vector -> then dispatcher multi vector to new flow emulator emit steps -> multi vector, save one redundant allocation
• simplify rv32im assign_opcode logic. e.g. assign_opcode!(ADD, AddInstruction<E>, add_config); -> assign_opcode!(AddInstruction<E>, add_config); and dispatch deal with routing for us
• Updated every instruction implementation.
• Removed the obsolete DummyInstruction scaffolding and trimmed tests/module exports to the ECALL-specific LargeEcallDummy, keeping DummyConfig only where it feeds those circuits.

Benchmark

test with 23817600 block, e2e remain no change

Component / Stage	Before (Time / %)	After (Time / %)	Δ Change
Total block	140s · 0.12% / 100%	140s · 0.15% / 100%	~ same
app.prove (total)	137s · 0.15% / 97.68%	137s · 0.15% / 97.65%	~ same

remain no change which is expected. Because 1st shard we still need to allocated vector, while shard > 0 pipeline gpu proving time is dominated

For detail breakdown assign_opcode_circuit

Shard Id	Before (s)	After (s)	Δ (s)
0	2.0319	1.8792	-0.1527
1	1.7117	1.5331	-0.1786
2	1.6976	1.5342	-0.1634
3	1.7091	1.5433	-0.1658
4	1.4510	1.3409	-0.1101
Avg	1.7203	1.5661	-0.1542 (~9.0%)

around 10% improvement