GitHub - sgong-0224/RISCV-PIPE: A simple 5-stage pipelined CPU implementation.

This repository was archived by the owner on May 11, 2025. It is now read-only.

Name		Name	Last commit message	Last commit date
Latest commit History 1 Commit
CPU		CPU
MEM		MEM
PDU		PDU
2_1_MUX.v		2_1_MUX.v
4_1_MUX.v		4_1_MUX.v
ALU.v		ALU.v
BR_UNIT.v		BR_UNIT.v
DECODER.v		DECODER.v
FWD_Ctrl_Unit.v		FWD_Ctrl_Unit.v
NPC_MUX.v		NPC_MUX.v
PC.v		PC.v
PipeReg_Ctrl_Unit.v		PipeReg_Ctrl_Unit.v
Pipeline_Stage_Reg.v		Pipeline_Stage_Reg.v
RF_WD_MUX.v		RF_WD_MUX.v
RegFile_WF.v		RegFile_WF.v
SL_UNIT.v		SL_UNIT.v
TOP.v		TOP.v