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1. ASIC-Design-of-32-bit-Pipelined-MIPS-Processor ASIC-Design-of-32-bit-Pipelined-MIPS-Processor Public

   32-bit 5-stage pipelined MIPS processor designed for ASIC flow. Includes hazard detection, data forwarding, branch handling, and verification-driven development. Synthesized and analyzed with STA a…

   Verilog

2. AXI-Lite-SoC-Subsystem-with-Verification AXI-Lite-SoC-Subsystem-with-Verification Public

   SystemVerilog

3. Custom-Pipelined-SoC-with-FFT-Crypto-Accelerator Custom-Pipelined-SoC-with-FFT-Crypto-Accelerator Public

   Verilog

4. 1-4-16-Bit-Hybrid-Adder 1-4-16-Bit-Hybrid-Adder Public

5. Aquabot Aquabot Public

   Automatic Motor Controller Based On Water Level

6. Self-Configurable-IoT-Satellite-Gateway-with-QoS-Traffic-Management Self-Configurable-IoT-Satellite-Gateway-with-QoS-Traffic-Management Public

   Python