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| 1 | +/* { dg-do assemble { target aarch64_asm_sme-b16b16_ok } } */ |
| 2 | +/* { dg-do compile { target { ! aarch64_asm_sme-b16b16_ok } } } */ |
| 3 | +/* { dg-final { check-function-bodies "**" "" "-DCHECK_ASM" } } */ |
| 4 | + |
| 5 | +#include "test_sme2_acle.h" |
| 6 | + |
| 7 | +#pragma GCC target "+sme-b16b16" |
| 8 | + |
| 9 | +/* |
| 10 | +** add_0_z0: |
| 11 | +** mov (w8|w9|w10|w11), #?0 |
| 12 | +** bfadd za\.h\[\1, 0, vgx2\], {z0\.h - z1\.h} |
| 13 | +** ret |
| 14 | +*/ |
| 15 | +TEST_ZA_XN (add_0_z0, svbfloat16x2_t, |
| 16 | + svadd_za16_bf16_vg1x2 (0, z0), |
| 17 | + svadd_za16_vg1x2 (0, z0)) |
| 18 | + |
| 19 | +/* |
| 20 | +** add_w0_z0: |
| 21 | +** mov (w8|w9|w10|w11), w0 |
| 22 | +** bfadd za\.h\[\1, 0, vgx2\], {z0\.h - z1\.h} |
| 23 | +** ret |
| 24 | +*/ |
| 25 | +TEST_ZA_XN (add_w0_z0, svbfloat16x2_t, |
| 26 | + svadd_za16_bf16_vg1x2 (w0, z0), |
| 27 | + svadd_za16_vg1x2 (w0, z0)) |
| 28 | + |
| 29 | +/* |
| 30 | +** add_w7_z0: |
| 31 | +** mov (w8|w9|w10|w11), w7 |
| 32 | +** bfadd za\.h\[\1, 0, vgx2\], {z0\.h - z1\.h} |
| 33 | +** ret |
| 34 | +*/ |
| 35 | +TEST_ZA_XN (add_w7_z0, svbfloat16x2_t, |
| 36 | + svadd_za16_bf16_vg1x2 (w7, z0), |
| 37 | + svadd_za16_vg1x2 (w7, z0)) |
| 38 | + |
| 39 | +/* |
| 40 | +** add_w8_z0: |
| 41 | +** bfadd za\.h\[w8, 0, vgx2\], {z0\.h - z1\.h} |
| 42 | +** ret |
| 43 | +*/ |
| 44 | +TEST_ZA_XN (add_w8_z0, svbfloat16x2_t, |
| 45 | + svadd_za16_bf16_vg1x2 (w8, z0), |
| 46 | + svadd_za16_vg1x2 (w8, z0)) |
| 47 | + |
| 48 | +/* |
| 49 | +** add_w11_z0: |
| 50 | +** bfadd za\.h\[w11, 0, vgx2\], {z0\.h - z1\.h} |
| 51 | +** ret |
| 52 | +*/ |
| 53 | +TEST_ZA_XN (add_w11_z0, svbfloat16x2_t, |
| 54 | + svadd_za16_bf16_vg1x2 (w11, z0), |
| 55 | + svadd_za16_vg1x2 (w11, z0)) |
| 56 | + |
| 57 | + |
| 58 | +/* |
| 59 | +** add_w12_z0: |
| 60 | +** mov (w8|w9|w10|w11), w12 |
| 61 | +** bfadd za\.h\[\1, 0, vgx2\], {z0\.h - z1\.h} |
| 62 | +** ret |
| 63 | +*/ |
| 64 | +TEST_ZA_XN (add_w12_z0, svbfloat16x2_t, |
| 65 | + svadd_za16_bf16_vg1x2 (w12, z0), |
| 66 | + svadd_za16_vg1x2 (w12, z0)) |
| 67 | + |
| 68 | +/* |
| 69 | +** add_w8p7_z0: |
| 70 | +** bfadd za\.h\[w8, 7, vgx2\], {z0\.h - z1\.h} |
| 71 | +** ret |
| 72 | +*/ |
| 73 | +TEST_ZA_XN (add_w8p7_z0, svbfloat16x2_t, |
| 74 | + svadd_za16_bf16_vg1x2 (w8 + 7, z0), |
| 75 | + svadd_za16_vg1x2 (w8 + 7, z0)) |
| 76 | + |
| 77 | +/* |
| 78 | +** add_w8p8_z0: |
| 79 | +** add (w8|w9|w10|w11), w8, #?8 |
| 80 | +** bfadd za\.h\[\1, 0, vgx2\], {z0\.h - z1\.h} |
| 81 | +** ret |
| 82 | +*/ |
| 83 | +TEST_ZA_XN (add_w8p8_z0, svbfloat16x2_t, |
| 84 | + svadd_za16_bf16_vg1x2 (w8 + 8, z0), |
| 85 | + svadd_za16_vg1x2 (w8 + 8, z0)) |
| 86 | + |
| 87 | +/* |
| 88 | +** add_w8m1_z0: |
| 89 | +** sub (w8|w9|w10|w11), w8, #?1 |
| 90 | +** bfadd za\.h\[\1, 0, vgx2\], {z0\.h - z1\.h} |
| 91 | +** ret |
| 92 | +*/ |
| 93 | +TEST_ZA_XN (add_w8m1_z0, svbfloat16x2_t, |
| 94 | + svadd_za16_bf16_vg1x2 (w8 - 1, z0), |
| 95 | + svadd_za16_vg1x2 (w8 - 1, z0)) |
| 96 | + |
| 97 | +/* |
| 98 | +** add_w8_z18: |
| 99 | +** bfadd za\.h\[w8, 0, vgx2\], {z18\.h - z19\.h} |
| 100 | +** ret |
| 101 | +*/ |
| 102 | +TEST_ZA_XN (add_w8_z18, svbfloat16x2_t, |
| 103 | + svadd_za16_bf16_vg1x2 (w8, z18), |
| 104 | + svadd_za16_vg1x2 (w8, z18)) |
| 105 | + |
| 106 | +/* Leave the assembler to check for correctness for misaligned registers. */ |
| 107 | + |
| 108 | +/* |
| 109 | +** add_w8_z23: |
| 110 | +** mov [^\n]+ |
| 111 | +** mov [^\n]+ |
| 112 | +** bfadd za\.h\[w8, 0, vgx2\], [^\n]+ |
| 113 | +** ret |
| 114 | +*/ |
| 115 | +TEST_ZA_XN (add_w8_z23, svbfloat16x2_t, |
| 116 | + svadd_za16_bf16_vg1x2 (w8, z23), |
| 117 | + svadd_za16_vg1x2 (w8, z23)) |
| 118 | + |
| 119 | +/* |
| 120 | +** add_w8_z28: |
| 121 | +** bfadd za\.h\[w8, 0, vgx2\], {z28\.h - z29\.h} |
| 122 | +** ret |
| 123 | +*/ |
| 124 | +TEST_ZA_XN (add_w8_z28, svbfloat16x2_t, |
| 125 | + svadd_za16_bf16_vg1x2 (w8, z28), |
| 126 | + svadd_za16_vg1x2 (w8, z28)) |
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