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yulong18yulong18
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Rename intrinsics function basename
1 parent e5ff754 commit ce66c73

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7 files changed

+63
-59
lines changed

7 files changed

+63
-59
lines changed

‎gcc/config/riscv/riscv-vector-builtins-bases.cc‎

Lines changed: 30 additions & 25 deletions
Original file line numberDiff line numberDiff line change
@@ -721,12 +721,17 @@ class vfnrclip : public function_base
721721

722722
rtx expand (function_expander &e) const override
723723
{
724-
if (e.op_info->op == OP_TYPE_f_qf)
725-
{
726-
return e.use_exact_insn (
724+
if (e.op_info->op == OP_TYPE_x_f_qf)
725+
{
726+
return e.use_exact_insn (
727727
code_for_pred_fnr_clip (ZERO_EXTEND, e.vector_mode ()));
728-
gcc_unreachable ();
729-
}
728+
}
729+
if (e.op_info->op == OP_TYPE_xu_f_qf)
730+
{
731+
return e.use_exact_insn (
732+
code_for_pred_fnr_clip_scalar (ZERO_EXTEND, e.vector_mode ()));
733+
}
734+
gcc_unreachable ();
730735
}
731736
};
732737

@@ -908,10 +913,10 @@ class vqmacc : public function_base
908913
{
909914
if (e.op_info->op == OP_TYPE_4x8x4)
910915
return e.use_widen_ternop_insn (
911-
code_for_pred_quad_mul_plus_qoq (SIGN_EXTEND, e.vector_mode ()));
916+
code_for_pred_matrix_mul_plus_qoq (SIGN_EXTEND, e.vector_mode ()));
912917
if (e.op_info->op == OP_TYPE_2x8x2)
913918
return e.use_widen_ternop_insn (
914-
code_for_pred_quad_mul_plus_dod (SIGN_EXTEND, e.vector_mode ()));
919+
code_for_pred_matrix_mul_plus_dod (SIGN_EXTEND, e.vector_mode ()));
915920
gcc_unreachable ();
916921
}
917922
};
@@ -930,10 +935,10 @@ class vqmaccu : public function_base
930935
{
931936
if (e.op_info->op == OP_TYPE_4x8x4)
932937
return e.use_widen_ternop_insn (
933-
code_for_pred_quad_mul_plus_qoq (ZERO_EXTEND, e.vector_mode ()));
938+
code_for_pred_matrix_mul_plus_qoq (ZERO_EXTEND, e.vector_mode ()));
934939
if (e.op_info->op == OP_TYPE_2x8x2)
935940
return e.use_widen_ternop_insn (
936-
code_for_pred_quad_mul_plus_dod (SIGN_EXTEND, e.vector_mode ()));
941+
code_for_pred_matrix_mul_plus_dod (SIGN_EXTEND, e.vector_mode ()));
937942
gcc_unreachable ();
938943
}
939944
};
@@ -952,10 +957,10 @@ class vqmaccsu : public function_base
952957
{
953958
if (e.op_info->op == OP_TYPE_4x8x4)
954959
return e.use_widen_ternop_insn (
955-
code_for_pred_quad_mul_plussu_qoq (e.vector_mode ()));
960+
code_for_pred_matrix_mul_plussu_qoq (e.vector_mode ()));
956961
if (e.op_info->op == OP_TYPE_2x8x2)
957962
return e.use_widen_ternop_insn (
958-
code_for_pred_quad_mul_plussu_dod (e.vector_mode ()));
963+
code_for_pred_matrix_mul_plussu_dod (e.vector_mode ()));
959964
gcc_unreachable ();
960965
}
961966
};
@@ -974,10 +979,10 @@ class vqmaccus : public function_base
974979
{
975980
if (e.op_info->op == OP_TYPE_4x8x4)
976981
return e.use_widen_ternop_insn (
977-
code_for_pred_quad_mul_plusus_qoq (e.vector_mode ()));
982+
code_for_pred_matrix_mul_plusus_qoq (e.vector_mode ()));
978983
if (e.op_info->op == OP_TYPE_2x8x2)
979984
return e.use_widen_ternop_insn (
980-
code_for_pred_quad_mul_plusus_dod (e.vector_mode ()));
985+
code_for_pred_matrix_mul_plusus_dod (e.vector_mode ()));
981986
gcc_unreachable ();
982987
}
983988
};
@@ -2682,8 +2687,8 @@ static CONSTEXPR const sat_op<UNSPEC_VSSRL> vssrl_obj;
26822687
static CONSTEXPR const sat_op<UNSPEC_VSSRA> vssra_obj;
26832688
static CONSTEXPR const vnclip<UNSPEC_VNCLIP> vnclip_obj;
26842689
static CONSTEXPR const vnclip<UNSPEC_VNCLIPU> vnclipu_obj;
2685-
static CONSTEXPR const vfnrclip x_obj;
2686-
static CONSTEXPR const vfnrclip xu_obj;
2690+
static CONSTEXPR const vfnrclip sf_vfnrclip_x_obj;
2691+
static CONSTEXPR const vfnrclip sf_vfnrclip_xu_obj;
26872692
static CONSTEXPR const mask_logic<AND> vmand_obj;
26882693
static CONSTEXPR const mask_nlogic<AND> vmnand_obj;
26892694
static CONSTEXPR const mask_notlogic<AND> vmandn_obj;
@@ -2873,10 +2878,10 @@ static CONSTEXPR const th_loadstore_width<true, LST_INDEXED, UNSPEC_TH_VSUXB> vs
28732878
static CONSTEXPR const th_loadstore_width<true, LST_INDEXED, UNSPEC_TH_VSUXH> vsuxh_obj;
28742879
static CONSTEXPR const th_loadstore_width<true, LST_INDEXED, UNSPEC_TH_VSUXW> vsuxw_obj;
28752880
static CONSTEXPR const th_extract vext_x_v_obj;
2876-
static CONSTEXPR const vqmacc vqmacc_obj;
2877-
static CONSTEXPR const vqmaccu vqmaccu_obj;
2878-
static CONSTEXPR const vqmaccsu vqmaccsu_obj;
2879-
static CONSTEXPR const vqmaccsu vqmaccus_obj;
2881+
static CONSTEXPR const vqmacc sf_vqmacc_obj;
2882+
static CONSTEXPR const vqmaccu sf_vqmaccu_obj;
2883+
static CONSTEXPR const vqmaccsu sf_vqmaccsu_obj;
2884+
static CONSTEXPR const vqmaccsu sf_vqmaccus_obj;
28802885

28812886
/* Crypto Vector */
28822887
static CONSTEXPR const vandn vandn_obj;
@@ -3018,8 +3023,8 @@ BASE (vssra)
30183023
BASE (vssrl)
30193024
BASE (vnclip)
30203025
BASE (vnclipu)
3021-
BASE (x)
3022-
BASE (xu)
3026+
BASE (sf_vfnrclip_x)
3027+
BASE (sf_vfnrclip_xu)
30233028
BASE (vmand)
30243029
BASE (vmnand)
30253030
BASE (vmandn)
@@ -3209,10 +3214,10 @@ BASE (vsuxb)
32093214
BASE (vsuxh)
32103215
BASE (vsuxw)
32113216
BASE (vext_x_v)
3212-
BASE (vqmacc)
3213-
BASE (vqmaccu)
3214-
BASE (vqmaccsu)
3215-
BASE (vqmaccus)
3217+
BASE (sf_vqmacc)
3218+
BASE (sf_vqmaccu)
3219+
BASE (sf_vqmaccsu)
3220+
BASE (sf_vqmaccus)
32163221
/* Crypto vector */
32173222
BASE (vandn)
32183223
BASE (vbrev)

‎gcc/config/riscv/riscv-vector-builtins-bases.h‎

Lines changed: 6 additions & 6 deletions
Original file line numberDiff line numberDiff line change
@@ -122,8 +122,8 @@ extern const function_base *const vssra;
122122
extern const function_base *const vssrl;
123123
extern const function_base *const vnclip;
124124
extern const function_base *const vnclipu;
125-
extern const function_base *const x;
126-
extern const function_base *const xu;
125+
extern const function_base *const sf_vfnrclip_x;
126+
extern const function_base *const sf_vfnrclip_xu;
127127
extern const function_base *const vmand;
128128
extern const function_base *const vmnand;
129129
extern const function_base *const vmandn;
@@ -313,10 +313,10 @@ extern const function_base *const vsuxb;
313313
extern const function_base *const vsuxh;
314314
extern const function_base *const vsuxw;
315315
extern const function_base *const vext_x_v;
316-
extern const function_base *const vqmacc;
317-
extern const function_base *const vqmaccu;
318-
extern const function_base *const vqmaccsu;
319-
extern const function_base *const vqmaccus;
316+
extern const function_base *const sf_vqmacc;
317+
extern const function_base *const sf_vqmaccu;
318+
extern const function_base *const sf_vqmaccsu;
319+
extern const function_base *const sf_vqmaccus;
320320
/* Below function_base are Vectro Crypto*/
321321
extern const function_base *const vandn;
322322
extern const function_base *const vbrev;

‎gcc/config/riscv/riscv-vector-builtins-shapes.cc‎

Lines changed: 3 additions & 6 deletions
Original file line numberDiff line numberDiff line change
@@ -1297,8 +1297,7 @@ struct sf_vqmacc_def : public build_base
12971297
if (overloaded_p && !instance.base->can_be_overloaded_p (instance.pred))
12981298
return nullptr;
12991299

1300-
b.append_name ("__riscv_sf_");
1301-
b.append_name (instance.base_name);
1300+
b.append_base_name (instance.base_name);
13021301

13031302
/* vop_v --> vop_v_<type>. */
13041303
if (!overloaded_p)
@@ -1330,14 +1329,12 @@ struct sf_vfnrclip_def : public build_base
13301329
if (overloaded_p && !instance.base->can_be_overloaded_p (instance.pred))
13311330
return nullptr;
13321331

1333-
b.append_name ("__riscv_sf_vfnrclip_");
1334-
printf("aaaaaa %s\n", instance.base_name);
1335-
b.append_name (instance.base_name);
1332+
b.append_base_name (instance.base_name);
13361333

13371334
if (!overloaded_p)
13381335
{
13391336
/* vop --> vop_<op>. */
1340-
b.append_name (operand_suffixes[instance.op_info->op]);
1337+
b.append_name ("_f_qf");
13411338
/* vop_v --> vop_v_<type>. */
13421339
b.append_name (type_suffixes[instance.type.index].vector);
13431340
/* vop_<op> --> vop_<op>_<type>.

‎gcc/config/riscv/riscv-vector-builtins.cc‎

Lines changed: 6 additions & 5 deletions
Original file line numberDiff line numberDiff line change
@@ -2529,16 +2529,17 @@ static CONSTEXPR const rvv_op_info i_narrow_shift_vwx_ops
25292529
/* A static operand information for double demote type func (vector_type,
25302530
* shift_type) function registration. */
25312531
static CONSTEXPR const rvv_op_info u_clip_qf_ops
2532-
= {wextu_ops, /* Types */
2533-
OP_TYPE_f_qf, /* Suffix */
2534-
rvv_arg_type_info (RVV_BASE_double_trunc_unsigned_vector), /* Return type */
2532+
= {wextu_ops, /* Types */
2533+
OP_TYPE_xu_f_qf, /* Suffix */
2534+
rvv_arg_type_info (
2535+
RVV_BASE_double_trunc_unsigned_vector), /* Return type */
25352536
clip_args /* Args */};
25362537

25372538
/* A static operand information for double demote type func (vector_type,
25382539
* shift_type) function registration. */
25392540
static CONSTEXPR const rvv_op_info i_clip_qf_ops
2540-
= {wexti_ops, /* Types */
2541-
OP_TYPE_f_qf, /* Suffix */
2541+
= {wexti_ops, /* Types */
2542+
OP_TYPE_x_f_qf, /* Suffix */
25422543
rvv_arg_type_info (RVV_BASE_double_trunc_signed_vector), /* Return type */
25432544
clip_args /* Args */};
25442545

‎gcc/config/riscv/riscv-vector-builtins.def‎

Lines changed: 2 additions & 1 deletion
Original file line numberDiff line numberDiff line change
@@ -636,7 +636,8 @@ DEF_RVV_OP_TYPE (xu_w)
636636
DEF_RVV_OP_TYPE (s)
637637
DEF_RVV_OP_TYPE (4x8x4)
638638
DEF_RVV_OP_TYPE (2x8x2)
639-
DEF_RVV_OP_TYPE (f_qf)
639+
DEF_RVV_OP_TYPE (x_f_qf)
640+
DEF_RVV_OP_TYPE (xu_f_qf)
640641

641642
DEF_RVV_PRED_TYPE (ta)
642643
DEF_RVV_PRED_TYPE (tu)

‎gcc/config/riscv/sifive-vector-builtins-functions.def‎

Lines changed: 10 additions & 10 deletions
Original file line numberDiff line numberDiff line change
@@ -3,22 +3,22 @@
33
#endif
44

55
#define REQUIRED_EXTENSIONS XSFVQMACCQOQ_EXT
6-
DEF_RVV_FUNCTION (vqmaccu, sf_vqmacc, none_tu_preds, u_qqvv_ops)
7-
DEF_RVV_FUNCTION (vqmacc, sf_vqmacc, none_tu_preds, i_qqvv_ops)
8-
DEF_RVV_FUNCTION (vqmaccsu, sf_vqmacc, none_tu_preds, i_su_qqvv_ops)
9-
DEF_RVV_FUNCTION (vqmaccus, sf_vqmacc, none_tu_preds, i_us_qqvv_ops)
6+
DEF_RVV_FUNCTION (sf_vqmaccu, sf_vqmacc, none_tu_preds, u_qqvv_ops)
7+
DEF_RVV_FUNCTION (sf_vqmacc, sf_vqmacc, none_tu_preds, i_qqvv_ops)
8+
DEF_RVV_FUNCTION (sf_vqmaccsu, sf_vqmacc, none_tu_preds, i_su_qqvv_ops)
9+
DEF_RVV_FUNCTION (sf_vqmaccus, sf_vqmacc, none_tu_preds, i_us_qqvv_ops)
1010
#undef REQUIRED_EXTENSIONS
1111

1212
#define REQUIRED_EXTENSIONS XSFVQMACCDOD_EXT
13-
DEF_RVV_FUNCTION (vqmaccu, sf_vqmacc, none_tu_preds, u_qdvv_ops)
14-
DEF_RVV_FUNCTION (vqmacc, sf_vqmacc, none_tu_preds, i_qdvv_ops)
15-
DEF_RVV_FUNCTION (vqmaccsu, sf_vqmacc, none_tu_preds, i_su_qdvv_ops)
16-
DEF_RVV_FUNCTION (vqmaccus, sf_vqmacc, none_tu_preds, i_us_qdvv_ops)
13+
DEF_RVV_FUNCTION (sf_vqmaccu, sf_vqmacc, none_tu_preds, u_qdvv_ops)
14+
DEF_RVV_FUNCTION (sf_vqmacc, sf_vqmacc, none_tu_preds, i_qdvv_ops)
15+
DEF_RVV_FUNCTION (sf_vqmaccsu, sf_vqmacc, none_tu_preds, i_su_qdvv_ops)
16+
DEF_RVV_FUNCTION (sf_vqmaccus, sf_vqmacc, none_tu_preds, i_us_qdvv_ops)
1717
#undef REQUIRED_EXTENSIONS
1818

1919
#define REQUIRED_EXTENSIONS XSFVFNRCLIPXFQF_EXT
20-
DEF_RVV_FUNCTION (xu, sf_vfnrclip, full_preds, u_clip_qf_ops)
21-
DEF_RVV_FUNCTION (x, sf_vfnrclip, full_preds, i_clip_qf_ops)
20+
DEF_RVV_FUNCTION (sf_vfnrclip_xu, sf_vfnrclip, full_preds, u_clip_qf_ops)
21+
DEF_RVV_FUNCTION (sf_vfnrclip_x, sf_vfnrclip, full_preds, i_clip_qf_ops)
2222

2323
#undef REQUIRED_EXTENSIONS
2424

‎gcc/config/riscv/sifive-vector.md‎

Lines changed: 6 additions & 6 deletions
Original file line numberDiff line numberDiff line change
@@ -1,4 +1,4 @@
1-
(define_insn "@pred_quad_mul_plus<su><mode>_qoq"
1+
(define_insn "@pred_matrix_mul_plus<su><mode>_qoq"
22
[(set (match_operand:V_SF 0 "register_operand" "=&vr")
33
(if_then_else:V_SF
44
(unspec:<VM>
@@ -22,7 +22,7 @@
2222
[(set_attr "type" "vsfmuladd")
2323
(set_attr "mode" "<MODE>")])
2424

25-
(define_insn "@pred_quad_mul_plussu<mode>_qoq"
25+
(define_insn "@pred_matrix_mul_plussu<mode>_qoq"
2626
[(set (match_operand:V_SF 0 "register_operand" "=&vr")
2727
(if_then_else:V_SF
2828
(unspec:<VM>
@@ -46,7 +46,7 @@
4646
[(set_attr "type" "vsfmuladd")
4747
(set_attr "mode" "<MODE>")])
4848

49-
(define_insn "@pred_quad_mul_plusus<mode>_qoq"
49+
(define_insn "@pred_matrix_mul_plusus<mode>_qoq"
5050
[(set (match_operand:V_SF 0 "register_operand" "=&vr")
5151
(if_then_else:V_SF
5252
(unspec:<VM>
@@ -70,7 +70,7 @@
7070
[(set_attr "type" "vsfmuladd")
7171
(set_attr "mode" "<MODE>")])
7272

73-
(define_insn "@pred_quad_mul_plus<su><mode>_dod"
73+
(define_insn "@pred_matrix_mul_plus<su><mode>_dod"
7474
[(set (match_operand:V_SF 0 "register_operand" "=&vr")
7575
(if_then_else:V_SF
7676
(unspec:<VM>
@@ -94,7 +94,7 @@
9494
[(set_attr "type" "vsfmuladd")
9595
(set_attr "mode" "<MODE>")])
9696

97-
(define_insn "@pred_quad_mul_plussu<mode>_dod"
97+
(define_insn "@pred_matrix_mul_plussu<mode>_dod"
9898
[(set (match_operand:V_SF 0 "register_operand" "=&vr")
9999
(if_then_else:V_SF
100100
(unspec:<VM>
@@ -118,7 +118,7 @@
118118
[(set_attr "type" "vsfmuladd")
119119
(set_attr "mode" "<MODE>")])
120120

121-
(define_insn "@pred_quad_mul_plusus<mode>_dod"
121+
(define_insn "@pred_matrix_mul_plusus<mode>_dod"
122122
[(set (match_operand:V_SF 0 "register_operand" "=&vr")
123123
(if_then_else:V_SF
124124
(unspec:<VM>

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