@@ -95,15 +95,11 @@ void* _configureADCLowSide(const void* driver_params, const int pinA,const int p
95
95
void _driverSyncLowSide (void * driver_params, void * cs_params){
96
96
// high side registers enable interrupt
97
97
// MCPWM[MCPWM_UNIT_0]->int_ena.timer0_tez_int_ena = true;//A PWM timer 0 TEP event will trigger this interrupt
98
- // MCPWM[MCPWM_UNIT_0]->int_ena.timer1_tez_int_ena = true;//A PWM timer 1 TEP event will trigger this interrupt
99
- // if( _isset(_pinC) ) MCPWM[MCPWM_UNIT_0]->int_ena.timer2_tez_int_ena = true;//A PWM timer 2 TEP event will trigger this interrupt
100
98
101
99
// low-side register enable interrupt
102
100
mcpwm_dev_t * mcpwm_dev = ((ESP32MCPWMDriverParams*)driver_params)->mcpwm_dev ;
103
101
mcpwm_unit_t mcpwm_unit = ((ESP32MCPWMDriverParams*)driver_params)->mcpwm_unit ;
104
102
mcpwm_dev->int_ena .timer0_tep_int_ena = true ;// A PWM timer 0 TEP event will trigger this interrupt
105
- mcpwm_dev->int_ena .timer1_tep_int_ena = true ;// A PWM timer 1 TEP event will trigger this interrupt
106
- if ( _isset (_pinC) ) mcpwm_dev->int_ena .timer2_tep_int_ena = true ;// A PWM timer 2 TEP event will trigger this interrupt
107
103
if (mcpwm_unit == MCPWM_UNIT_0)
108
104
mcpwm_isr_register (mcpwm_unit, mcpwm0_isr_handler, NULL , ESP_INTR_FLAG_IRAM, NULL ); // Set ISR Handler
109
105
else
@@ -113,77 +109,63 @@ void _driverSyncLowSide(void* driver_params, void* cs_params){
113
109
// Read currents when interrupt is triggered
114
110
static void IRAM_ATTR mcpwm0_isr_handler (void *){
115
111
// // high side
116
- // uint32_t mcpwm_intr_status_0 = MCPWM[MCPWM_UNIT_0]->int_st.timer0_tez_int_st;
117
- // uint32_t mcpwm_intr_status_1 = MCPWM[MCPWM_UNIT_0]->int_st.timer1_tez_int_st;
118
- // uint32_t mcpwm_intr_status_2 = _isset(_pinC) ? MCPWM[MCPWM_UNIT_0]->int_st.timer2_tez_int_st : 0;
119
-
112
+ // uint32_t mcpwm_intr_status_0 = MCPWM0.int_st.timer0_tez_int_st;
113
+
120
114
// low side
121
- uint32_t mcpwm_intr_status_0 = MCPWM0.int_st .timer0_tep_int_st ;
122
- uint32_t mcpwm_intr_status_1 = MCPWM0.int_st .timer1_tep_int_st ;
123
- uint32_t mcpwm_intr_status_2 = _isset (_pinC) ? MCPWM0.int_st .timer2_tep_int_st : 0 ;
124
-
125
- switch (currentState)
126
- {
127
- case 1 :
128
- if (mcpwm_intr_status_0 > 0 ) a1 = adcRead (_pinA);
129
- currentState = 2 ;
130
- break ;
131
- case 2 :
132
- if (mcpwm_intr_status_1 > 0 ) a2 = adcRead (_pinB);
133
- currentState = _isset (_pinC) ? 3 : 1 ;
134
- break ;
135
- case 3 :
136
- if (mcpwm_intr_status_2 > 0 ) a3 = adcRead (_pinC);
137
- currentState = 1 ;
138
- break ;
115
+ uint32_t mcpwm_intr_status = MCPWM0.int_st .timer0_tep_int_st ;
116
+ if (mcpwm_intr_status){
117
+ switch (currentState)
118
+ {
119
+ case 1 :
120
+ a1 = adcRead (_pinA);
121
+ currentState = 2 ;
122
+ break ;
123
+ case 2 :
124
+ a2 = adcRead (_pinB);
125
+ currentState = _isset (_pinC) ? 3 : 1 ;
126
+ break ;
127
+ case 3 :
128
+ a3 = adcRead (_pinC);
129
+ currentState = 1 ;
130
+ break ;
131
+ }
139
132
}
140
-
141
133
// high side
142
- // MCPWM[MCPWM_UNIT_0]->int_clr.timer0_tez_int_clr = mcpwm_intr_status_0;
143
- // MCPWM[MCPWM_UNIT_0]->int_clr.timer1_tez_int_clr = mcpwm_intr_status_1;
144
- // if( _isset(_pinC) ) MCPWM[MCPWM_UNIT_0]->int_clr.timer2_tez_int_clr = mcpwm_intr_status_2;
134
+ // MCPWM0.int_clr.timer0_tez_int_clr = mcpwm_intr_status_0;
135
+
145
136
// low side
146
- MCPWM0.int_clr .timer0_tep_int_clr = mcpwm_intr_status_0;
147
- MCPWM0.int_clr .timer1_tep_int_clr = mcpwm_intr_status_1;
148
- if ( _isset (_pinC) ) MCPWM0.int_clr .timer2_tep_int_clr = mcpwm_intr_status_2;
137
+ MCPWM0.int_clr .timer0_tep_int_clr = mcpwm_intr_status;
149
138
}
150
139
151
140
// Read currents when interrupt is triggered
152
141
static void IRAM_ATTR mcpwm1_isr_handler (void *){
153
142
// // high side
154
- // uint32_t mcpwm_intr_status_0 = MCPWM[MCPWM_UNIT_0]->int_st.timer0_tez_int_st;
155
- // uint32_t mcpwm_intr_status_1 = MCPWM[MCPWM_UNIT_0]->int_st.timer1_tez_int_st;
156
- // uint32_t mcpwm_intr_status_2 = _isset(_pinC) ? MCPWM[MCPWM_UNIT_0]->int_st.timer2_tez_int_st : 0;
157
-
143
+ // uint32_t mcpwm_intr_status_0 = MCPWM1.int_st.timer0_tez_int_st;
144
+
158
145
// low side
159
- uint32_t mcpwm_intr_status_0 = MCPWM1.int_st .timer0_tep_int_st ;
160
- uint32_t mcpwm_intr_status_1 = MCPWM1.int_st .timer1_tep_int_st ;
161
- uint32_t mcpwm_intr_status_2 = _isset (_pinC) ? MCPWM1.int_st .timer2_tep_int_st : 0 ;
162
-
163
- switch (currentState)
164
- {
165
- case 1 :
166
- if (mcpwm_intr_status_0 > 0 ) a1 = adcRead (_pinA);
167
- currentState = 2 ;
168
- break ;
169
- case 2 :
170
- if (mcpwm_intr_status_1 > 0 ) a2 = adcRead (_pinB);
171
- currentState = _isset (_pinC) ? 3 : 1 ;
172
- break ;
173
- case 3 :
174
- if (mcpwm_intr_status_2 > 0 ) a3 = adcRead (_pinC);
175
- currentState = 1 ;
176
- break ;
146
+ uint32_t mcpwm_intr_status = MCPWM1.int_st .timer0_tep_int_st ;
147
+ if (mcpwm_intr_status){
148
+ switch (currentState)
149
+ {
150
+ case 1 :
151
+ a1 = adcRead (_pinA);
152
+ currentState = 2 ;
153
+ break ;
154
+ case 2 :
155
+ a2 = adcRead (_pinB);
156
+ currentState = _isset (_pinC) ? 3 : 1 ;
157
+ break ;
158
+ case 3 :
159
+ a3 = adcRead (_pinC);
160
+ currentState = 1 ;
161
+ break ;
162
+ }
177
163
}
178
-
179
164
// high side
180
- // MCPWM[MCPWM_UNIT_0]->int_clr.timer0_tez_int_clr = mcpwm_intr_status_0;
181
- // MCPWM[MCPWM_UNIT_0]->int_clr.timer1_tez_int_clr = mcpwm_intr_status_1;
182
- // if( _isset(_pinC) ) MCPWM[MCPWM_UNIT_0]->int_clr.timer2_tez_int_clr = mcpwm_intr_status_2;
165
+ // MCPWM1.int_clr.timer0_tez_int_clr = mcpwm_intr_status_0;
166
+
183
167
// low side
184
- MCPWM1.int_clr .timer0_tep_int_clr = mcpwm_intr_status_0;
185
- MCPWM1.int_clr .timer1_tep_int_clr = mcpwm_intr_status_1;
186
- if ( _isset (_pinC) ) MCPWM1.int_clr .timer2_tep_int_clr = mcpwm_intr_status_2;
168
+ MCPWM1.int_clr .timer0_tep_int_clr = mcpwm_intr_status;
187
169
}
188
170
189
171
0 commit comments