[BUG] esp32-s3 can't use nvs

[MGJ520]

nvs not good work,when i use simplefoc,this is a issue：

void _driverSyncLowSide(void* driver_params, void* cs_params){
    mcpwm_dev_t* mcpwm_dev = ((ESP32MCPWMDriverParams*)driver_params)->mcpwm_dev;
    mcpwm_unit_t mcpwm_unit = ((ESP32MCPWMDriverParams*)driver_params)->mcpwm_unit;
    mcpwm_dev->int_ena.timer0_tep_int_ena = true;//A PWM timer 0 TEP event will trigger this interrupt
    // mcpwm_dev->int_ena.timer0_tep_int_ena = true;//A PWM timer 0 TEZ event will trigger this interrupt
    if(mcpwm_unit == MCPWM_UNIT_0)
    {
        mcpwm_isr_register(mcpwm_unit, mcpwm0_isr_handler, NULL, ESP_INTR_FLAG_IRAM, NULL);  //Set ISR Handler
    }
     else
        mcpwm_isr_register(mcpwm_unit, mcpwm1_isr_handler, NULL, ESP_INTR_FLAG_IRAM, NULL);  //Set ISR Handler
}

Why does ESP_INTR_FLAG_IRAM affect NVS?

IRAM Interrupts Disable Flash Access:

If the ESP32 interrupt service routine (ISR) is placed in IRAM (using ESP_INTR_FLAG_IRAM), the CPU cannot access Flash during the execution of the ISR (because IRAM code must be executed without delay).

NVS operations (such as nvs_get_* and nvs_set_*) require Flash access. If an IRAM ISR is running, NVS operations may fail or cause a deadlock.

NVS Depends on Flash Operations:

NVS relies on SPI Flash at the lower level. Flash access may be blocked during IRAM ISR execution, leading to NVS read/write failures.

Interrupt Priority Issues:

If the MCPWM interrupt has a higher priority and is triggered frequently, it may prevent NVS operations from completing in a timely manner.

[runger1101001]

SimpleFOC needs the interrupts for current sensing. They are placed in IRAM to ensure they execute quickly, which is also important.

As a workaround I would suggest handling nvm access before initialising the current sense, if possible.
Since S3 MCU has two cores you could also investigate if it is possible to handle the SimpleFOC interrupts on one core, and the nvmram ones on the other.

Otherwise, if you have suggestions for an improvement that keeps the ADC performance but avoids this problem, I'd be interested to learn.

[MGJ520]

Hi，thank you,
1.Since S3 MCU has two cores you could also investigate if it is possible to handle the SimpleFOC interrupts on one core, and the nvmram ones on the other.
I try it,however it not work,the chip keeps restarting, triggering the watchdog
2.Otherwise, if you have suggestions for an improvement that keeps the ADC performance but avoids this problem, I'd be interested to learn.
my project need simplefoc to work with nvs at the same time,now,i no idea 😭

[uLipe]

@MGJ520 just a suggestion, why not buffer the next value to be written in the NVS at the RAM first then defer the actual NVS write to a high priority thread?

For example:

-> Save the next NVS entry plus its timestamp in the RAM during ISR -> Notify a high priority thread (it can have tthe priority in configMAX_PRIORITIES - 2) -> the thread actually moves the NVS data in the RAM to the flash.

I dont't think is a good idea to write to ESP32 flash during the ISR mostly because it will cause too much latency and CPU starvation since disabling the flash access may require flushing the I-CACHE, and execute only IRAM code, and after reenabling the -ICACHE some time will be required to fill it and while that the IROM code will be accessed in a form of QSPI operations, which are far slower than IRAM access.