bypassing surf.QsfpCdrDisable by default for U200

ruck314 · ruck314 · commit bbfdd6ed1740 · 2025-04-30T19:20:27.000-07:00
diff --git a/firmware/submodules/axi-pcie-core b/firmware/submodules/axi-pcie-core
@@ -1 +1 @@
-Subproject commit bccc46cb26a1d25eb519f9611d60e9418d6365da
+Subproject commit fd832dadeb55f66c8afdd1b5597f2ddf8b3de6e1
diff --git a/firmware/targets/XilinxAlveoU200/XilinxAlveoU200DmaLoopback/hdl/XilinxAlveoU200DmaLoopback.vhd b/firmware/targets/XilinxAlveoU200/XilinxAlveoU200DmaLoopback/hdl/XilinxAlveoU200DmaLoopback.vhd
@@ -125,10 +125,11 @@ begin
 
    U_Core : entity axi_pcie_core.XilinxAlveoU200Core
       generic map (
-         TPD_G             => TPD_G,
-         BUILD_INFO_G      => BUILD_INFO_G,
-         DMA_AXIS_CONFIG_G => DMA_AXIS_CONFIG_C,
-         DMA_SIZE_G        => DMA_SIZE_C)
+         TPD_G              => TPD_G,
+         QSFP_CDR_DISABLE_G => true,    -- < 25Gb/s/lane
+         BUILD_INFO_G       => BUILD_INFO_G,
+         DMA_AXIS_CONFIG_G  => DMA_AXIS_CONFIG_C,
+         DMA_SIZE_G         => DMA_SIZE_C)
       port map (
          ------------------------
          --  Top Level Interfaces
diff --git a/firmware/targets/XilinxAlveoU200/XilinxAlveoU200Pgp2b/hdl/XilinxAlveoU200Pgp2b.vhd b/firmware/targets/XilinxAlveoU200/XilinxAlveoU200Pgp2b/hdl/XilinxAlveoU200Pgp2b.vhd
@@ -172,6 +172,7 @@ begin
    U_Core : entity axi_pcie_core.XilinxAlveoU200Core
       generic map (
          TPD_G                => TPD_G,
+         QSFP_CDR_DISABLE_G   => true,  -- < 25Gb/s/lane
          ROGUE_SIM_EN_G       => ROGUE_SIM_EN_G,
          ROGUE_SIM_PORT_NUM_G => ROGUE_SIM_PORT_NUM_G,
          BUILD_INFO_G         => BUILD_INFO_G,
diff --git a/firmware/targets/XilinxAlveoU200/XilinxAlveoU200Pgp3_10Gbps/hdl/XilinxAlveoU200Pgp3_10Gbps.vhd b/firmware/targets/XilinxAlveoU200/XilinxAlveoU200Pgp3_10Gbps/hdl/XilinxAlveoU200Pgp3_10Gbps.vhd
@@ -173,6 +173,7 @@ begin
    U_Core : entity axi_pcie_core.XilinxAlveoU200Core
       generic map (
          TPD_G                => TPD_G,
+         QSFP_CDR_DISABLE_G   => true,  -- < 25Gb/s/lane
          ROGUE_SIM_EN_G       => ROGUE_SIM_EN_G,
          ROGUE_SIM_PORT_NUM_G => ROGUE_SIM_PORT_NUM_G,
          BUILD_INFO_G         => BUILD_INFO_G,
diff --git a/firmware/targets/XilinxAlveoU200/XilinxAlveoU200Pgp3_6Gbps/hdl/XilinxAlveoU200Pgp3_6Gbps.vhd b/firmware/targets/XilinxAlveoU200/XilinxAlveoU200Pgp3_6Gbps/hdl/XilinxAlveoU200Pgp3_6Gbps.vhd
@@ -173,6 +173,7 @@ begin
    U_Core : entity axi_pcie_core.XilinxAlveoU200Core
       generic map (
          TPD_G                => TPD_G,
+         QSFP_CDR_DISABLE_G   => true,  -- < 25Gb/s/lane
          ROGUE_SIM_EN_G       => ROGUE_SIM_EN_G,
          ROGUE_SIM_PORT_NUM_G => ROGUE_SIM_PORT_NUM_G,
          BUILD_INFO_G         => BUILD_INFO_G,
diff --git a/firmware/targets/XilinxAlveoU200/XilinxAlveoU200Pgp4_10Gbps/hdl/XilinxAlveoU200Pgp4_10Gbps.vhd b/firmware/targets/XilinxAlveoU200/XilinxAlveoU200Pgp4_10Gbps/hdl/XilinxAlveoU200Pgp4_10Gbps.vhd
@@ -172,6 +172,7 @@ begin
    U_Core : entity axi_pcie_core.XilinxAlveoU200Core
       generic map (
          TPD_G                => TPD_G,
+         QSFP_CDR_DISABLE_G   => true,  -- < 25Gb/s/lane
          ROGUE_SIM_EN_G       => ROGUE_SIM_EN_G,
          ROGUE_SIM_PORT_NUM_G => ROGUE_SIM_PORT_NUM_G,
          BUILD_INFO_G         => BUILD_INFO_G,
diff --git a/firmware/targets/XilinxAlveoU200/XilinxAlveoU200Pgp4_12Gbps/hdl/XilinxAlveoU200Pgp4_12Gbps.vhd b/firmware/targets/XilinxAlveoU200/XilinxAlveoU200Pgp4_12Gbps/hdl/XilinxAlveoU200Pgp4_12Gbps.vhd
@@ -172,6 +172,7 @@ begin
    U_Core : entity axi_pcie_core.XilinxAlveoU200Core
       generic map (
          TPD_G                => TPD_G,
+         QSFP_CDR_DISABLE_G   => true,  -- < 25Gb/s/lane
          ROGUE_SIM_EN_G       => ROGUE_SIM_EN_G,
          ROGUE_SIM_PORT_NUM_G => ROGUE_SIM_PORT_NUM_G,
          BUILD_INFO_G         => BUILD_INFO_G,
diff --git a/firmware/targets/XilinxAlveoU200/XilinxAlveoU200Pgp4_15Gbps/hdl/XilinxAlveoU200Pgp4_15Gbps.vhd b/firmware/targets/XilinxAlveoU200/XilinxAlveoU200Pgp4_15Gbps/hdl/XilinxAlveoU200Pgp4_15Gbps.vhd
@@ -172,6 +172,7 @@ begin
    U_Core : entity axi_pcie_core.XilinxAlveoU200Core
       generic map (
          TPD_G                => TPD_G,
+         QSFP_CDR_DISABLE_G   => true,  -- < 25Gb/s/lane
          ROGUE_SIM_EN_G       => ROGUE_SIM_EN_G,
          ROGUE_SIM_PORT_NUM_G => ROGUE_SIM_PORT_NUM_G,
          BUILD_INFO_G         => BUILD_INFO_G,
diff --git a/firmware/targets/XilinxAlveoU200/XilinxAlveoU200Pgp4_6Gbps/hdl/XilinxAlveoU200Pgp4_6Gbps.vhd b/firmware/targets/XilinxAlveoU200/XilinxAlveoU200Pgp4_6Gbps/hdl/XilinxAlveoU200Pgp4_6Gbps.vhd
@@ -172,6 +172,7 @@ begin
    U_Core : entity axi_pcie_core.XilinxAlveoU200Core
       generic map (
          TPD_G                => TPD_G,
+         QSFP_CDR_DISABLE_G   => true,  -- < 25Gb/s/lane
          ROGUE_SIM_EN_G       => ROGUE_SIM_EN_G,
          ROGUE_SIM_PORT_NUM_G => ROGUE_SIM_PORT_NUM_G,
          BUILD_INFO_G         => BUILD_INFO_G,
diff --git a/firmware/targets/XilinxAlveoU200/XilinxAlveoU200PrbsTester/hdl/XilinxAlveoU200PrbsTester.vhd b/firmware/targets/XilinxAlveoU200/XilinxAlveoU200PrbsTester/hdl/XilinxAlveoU200PrbsTester.vhd
@@ -135,12 +135,13 @@ begin
    -----------------------
    U_Core : entity axi_pcie_core.XilinxAlveoU200Core
       generic map (
-         TPD_G             => TPD_G,
-         BUILD_INFO_G      => BUILD_INFO_G,
-         DMA_AXIS_CONFIG_G => DMA_AXIS_CONFIG_C,
+         TPD_G              => TPD_G,
+         QSFP_CDR_DISABLE_G => true,    -- < 25Gb/s/lane
+         BUILD_INFO_G       => BUILD_INFO_G,
+         DMA_AXIS_CONFIG_G  => DMA_AXIS_CONFIG_C,
          -- DMA_BURST_BYTES_G => 4096,
-         DMA_BURST_BYTES_G => 256,
-         DMA_SIZE_G        => DMA_SIZE_C)
+         DMA_BURST_BYTES_G  => 256,
+         DMA_SIZE_G         => DMA_SIZE_C)
       port map (
          ------------------------
          --  Top Level Interfaces
