samples: cores3 spi lcd: ensure overlay and SPI init

[soburi]

Summary

• set the sample's overlay explicitly and rename the LCD node to avoid conflicts with the SoC LCD_CAM block
• build the SPI transaction descriptor manually with GPIO-based CS control since zephyr,spi-device lacks bindings for timing properties
• enable SPI support in the sample configuration so the ESP32-S3 controller device is instantiated

Testing

• west build -b m5stack_cores3/esp32s3/procpu samples/boards/espressif/m5stack_cores3_spi_lcd_raw --pristine -- -DZEPHYR_EXTRA_MODULES=/workspace/modules/hal/espressif

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https://chatgpt.com/codex/tasks/task_e_68e9df8d58f08322bb11568167fe9534

[chatgpt-codex-connector]

💡 Codex Review

zephyr/drivers/spi/spi_esp32_spim.c

Lines 238 to 255 in 9b24ecf

	/* send data */
	spi_hal_user_start(hal);
	spi_context_update_tx(&data->ctx, data->dfs, transfer_len_frames);
	while (!spi_hal_usr_is_done(hal)) {
	/* nop */
	}
	if (!cfg->dma_enabled) {
	/* read data */
	spi_hal_fetch_result(hal);
	}
	if (rx_temp) {
	memcpy(&ctx->rx_buf[0], rx_temp, transfer_len_bytes);
	}
	spi_context_update_rx(&data->ctx, data->dfs, transfer_len_frames);

Adjust tx/rx context for unaligned frame sizes

After computing transfer_len_bytes for the active chunk, the code still calls spi_context_update_tx(&data->ctx, data->dfs, transfer_len_frames) and the equivalent for RX. data->dfs is DIV_ROUND_UP(dfs_bits, 8), so for a 9‑bit word data->dfs becomes 2 bytes even though the transfer only consumes ceil(frames * 9 / 8) bytes (e.g. 36 bytes for 32 frames). The context update therefore advances the buffer pointer by frames * data->dfs (64 bytes in the example), skipping the remainder of the bit‑packed data and causing the rest of the message to be dropped. The new sample packs 9‑bit words densely, so any unaligned word size will transmit only part of the buffer. The update needs to use the actual byte count (transfer_len_bytes) when dfs_bits % 8 != 0 or the feature will corrupt transfers.

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