CHB:ARM:disassembly for STCL/STC2/LDC2

Author: sipma

CodeHawk/CHB/bchlibarm32/bCHDisassembleARMInstruction.ml

@@ -1836,6 +1836,23 @@ let parse_misc_6_type (instr: doubleword_int) (cond: int) =
      (* FSTMIAX<c> <Rn>, <list> *)
      FStoreMultipleIncrementAfter (false, c, rn RD, rl RD, mem WR)
 
+  (* <cc><6>01D10<rn><cd><cp><-imm8-> *)   (* STCL - A1 *)
+  | (1, 2, 1) ->
+      let isindex = (bv 24) = 1 in
+      let isadd = (bv 23) = 1 in
+      let iswback = (bv 21) = 1 in
+      let islong = (bv 22) = 1 in
+      let crd = b 15 12 in
+      let coproc = b 11 8 in
+      let imm32 = 4 * (b 7 0) in
+      let offset = ARMImmOffset imm32 in
+      let rnreg = get_arm_reg (b 19 16) in
+      let mem =
+        mk_arm_offset_address_op
+          ~align:4 rnreg offset ~isadd ~isindex ~iswback in
+      (* STC{L}<c> <coproc>, <CRd>, [<Rn>, #+/-<imm>]{!} *)
+      StoreCoprocessor (islong, false, c, coproc, crd, mem WR, None)
+
   (* <cc><6>01D00<rn><vd><11><-imm8-> *)   (* VSTM - A1-wb *)
   | (1, 2, 11) when (bv 0) = 0 ->
      let d = prefix_bit (bv 22) (b 15 12) in
@@ -4750,6 +4767,27 @@ let parse_cond15 (instr: doubleword_int) (iaddr: doubleword_int) =
      (* BLX <label> *)
      BranchLinkExchange(cc, tgtop)
 
+  (* <15>110PUDW0<rn><cd><cp><-imm8-> *)(* STC2{L}<c> <coproc>,<CRd>,[<Rn>, #+/-imm] *)
+  | (25, (2 | 3), 1, 0, 0) ->
+      let isindex = (bv 24) = 1 in
+      let isadd = (bv 23) = 1 in
+      let iswback = (bv 21) = 1 in
+      let islong = (bv 22) = 1 in
+      let crd = b 15 12 in
+      let coproc = b 11 8 in
+      let imm32 = 4 * (b 7 0) in
+      let offset = ARMImmOffset imm32 in
+      let rnreg = get_arm_reg (b 19 16) in
+      let mem =
+        mk_arm_offset_address_op
+          ~align:4 rnreg offset ~isadd ~isindex ~iswback in
+      if (bv 20) = 0 then
+        (* STC{L}<c> <coproc>, <CRd>, [<Rn>, #+/-<imm>]{!} *)
+        StoreCoprocessor (islong, true, cc, coproc, crd, mem WR, None)
+      else
+        (* LDC{L}<c> <coproc>, <CRd>, [<Rn>, #+-<imm>}{!} *)
+        LoadCoprocessor (islong, true, cc, coproc, crd, mem RD, None)
+
   | (x, y, z, q, v) ->
      NotRecognized (
          "arm:cond15:"

CodeHawk/CHB/bchlibarm32/bCHDisassembleThumbInstruction.ml

@@ -828,10 +828,10 @@ let parse_thumb32_29_2
           ~align:4 rnreg offset ~isadd ~isindex ~iswback in
       if (bv 20) = 0 then
         (* STC{L}<c> <coproc>, <CRd>, [<Rn>, #+/-<imm>]{!} *)
-        StoreCoprocessor (islong, false, cc, coproc, crd, mem WR, None)
+        StoreCoprocessor (islong, true, cc, coproc, crd, mem WR, None)
       else
         (* LDC{L}<c> <coproc>, <CRd>, [<Rn>, #+-<imm>}{!} *)
-        LoadCoprocessor (islong, false, cc, coproc, crd, mem RD, None)
+        LoadCoprocessor (islong, true, cc, coproc, crd, mem RD, None)
   else
     let selector = b 24 23 in
     let isz = b 21 20 in

CodeHawk/CHT/CHB_tests/bchlibarm32_tests/txbchlibarm32/bCHDisassembleARMInstructionTest.ml

@@ -48,7 +48,7 @@ open BCHDisassembleARMInstruction
 
 
 let testname = "bCHDisassembleARMInstructionTest"
-let lastupdated = "2024-10-31"
+let lastupdated = "2025-06-09"
 
 
 let make_dw (s: string) = TR.tget_ok (string_to_doubleword s)
@@ -78,6 +78,7 @@ let arm_basic () =
       ("CMP",    "010050e3", "CMP            R0, #1");
       ("CMPNE",  "00005111", "CMPNE          R1, R0");
       ("DMB",    "5bf07ff5", "DMB            ISH");
+      ("LDC2",   "0181b0fc", "LDC2           p1, c8, [R0],#4");
       ("LDCL",   "02a1f0ec", "LDCL           p1, c10, [R0],#8");
       ("LDM",    "1c5091e8", "LDM            R1, {R2,R3,R4,R12,LR}");
       ("LDR",    "001094e5", "LDR            R1, [R4]");
@@ -125,6 +126,8 @@ let arm_basic () =
       ("SMULL",  "9310c7e0", "SMULL          R1, R7, R3, R0");
       ("SMULWB", "a90523e1", "SMULWB         R3, R9, R5");
       ("SMULWT", "e00c23e1", "SMULWT         R3, R0, R12");
+      ("STC2",   "0181a0fc", "STC2           p1, c8, [R0],#4");
+      ("STCL",   "0201e0ec", "STCL           p1, c0, [R0],#8");
       ("STM",    "1a0080e8", "STM            R0, {R1,R3,R4}");
       ("STMDA",  "030003e8", "STMDA          R3, {R0,R1}");
       ("STMIB",  "21078de9", "STMIB          SP, {R0,R5,R8,R9,R10}");