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update deps
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9 files changed

+97
-140
lines changed

9 files changed

+97
-140
lines changed

‎.vscode/settings.json‎

Lines changed: 2 additions & 2 deletions
Original file line numberDiff line numberDiff line change
@@ -1,6 +1,6 @@
11
{
22
"rust.all_targets": false,
3-
"rust.target": "thumbv7em-none-eabi",
3+
"rust.target": "thumbv7m-none-eabi",
44
"rust.all_features": false,
55
"rust.features": [
66
"rtic",
@@ -10,7 +10,7 @@
1010
"rust-analyzer.checkOnSave.allTargets": false,
1111
"rust-analyzer.checkOnSave.extraArgs": [
1212
"--target",
13-
"thumbv7em-none-eabi"
13+
"thumbv7m-none-eabi"
1414
],
1515
"rust-analyzer.cargo.features": [
1616
"rtic",

‎Cargo.toml‎

Lines changed: 9 additions & 9 deletions
Original file line numberDiff line numberDiff line change
@@ -18,15 +18,15 @@ features = ["stm32f103", "rt"]
1818
default-target = "x86_64-unknown-linux-gnu"
1919

2020
[dependencies]
21-
cortex-m = "0.7.4"
21+
cortex-m = "0.7.6"
2222
cortex-m-rt = "0.7.1"
2323
nb = "1"
24-
stm32f1 = "0.14.0"
24+
stm32f1 = "0.15.1"
2525
embedded-dma = "0.2.0"
2626
bxcan = "0.7"
2727
void = { default-features = false, version = "1.0.2" }
2828
embedded-hal = { features = ["unproven"], version = "0.2.7" }
29-
fugit = "0.3.5"
29+
fugit = "0.3.6"
3030
fugit-timer = "0.1.3"
3131
rtic-monotonic = { version = "1.0", optional = true }
3232
bitflags = "1.3.2"
@@ -37,12 +37,12 @@ optional = true
3737

3838
[dev-dependencies]
3939
panic-halt = "0.2.0"
40-
panic-semihosting = "0.5.6"
41-
panic-itm = "0.4.1"
42-
cortex-m-rtic = "1.0.0"
43-
cortex-m-semihosting = "0.3.7"
44-
heapless = "0.7.10"
45-
mfrc522 = "0.2.0"
40+
panic-semihosting = "0.6.0"
41+
panic-itm = "0.4.2"
42+
cortex-m-rtic = "1.1.3"
43+
cortex-m-semihosting = "0.5.0"
44+
heapless = "0.7.16"
45+
mfrc522 = "0.3.0"
4646
usb-device = "0.2.8"
4747
usbd-serial = "0.1.1"
4848
unwrap-infallible = "0.1.5"

‎examples/i2c-bme280/Cargo.toml‎

Lines changed: 6 additions & 6 deletions
Original file line numberDiff line numberDiff line change
@@ -8,15 +8,15 @@ edition = "2018"
88
publish = false
99

1010
[dependencies]
11-
bme280 = "0.2.1"
12-
cortex-m-semihosting = "0.3.3"
13-
panic-semihosting = "0.5.2"
14-
cortex-m-rt = "0.6.8"
15-
cortex-m = "0.6.0"
11+
bme280 = "0.3.0"
12+
cortex-m-semihosting = "0.5.0"
13+
panic-semihosting = "0.6.0"
14+
cortex-m-rt = "0.7.1"
15+
cortex-m = "0.7.6"
1616

1717
[dependencies.stm32f1xx-hal]
1818
path = "../.."
19-
version = "0.7.0"
19+
version = "0.9.0"
2020
features = ["stm32f103", "rt", "stm32-usbd"]
2121

2222
[profile.dev]

‎examples/i2c-bme280/src/main.rs‎

Lines changed: 8 additions & 9 deletions
Original file line numberDiff line numberDiff line change
@@ -21,10 +21,9 @@
2121
use cortex_m_semihosting::hprintln;
2222
use panic_semihosting as _;
2323

24-
use bme280::BME280;
24+
use bme280::i2c::BME280;
2525
use cortex_m_rt::entry;
2626
use stm32f1xx_hal::{
27-
delay::Delay,
2827
i2c::{BlockingI2c, DutyCycle, Mode},
2928
pac,
3029
prelude::*,
@@ -40,7 +39,7 @@ fn main() -> ! {
4039
// Take ownership over the raw flash and rcc devices and convert them into the corresponding
4140
// HAL structs
4241
let mut flash = dp.FLASH.constrain();
43-
let mut rcc = dp.RCC.constrain();
42+
let rcc = dp.RCC.constrain();
4443
let mut afio = dp.AFIO.constrain();
4544
// Freeze the configuration of all the clocks in the system and store the frozen frequencies in
4645
// `clocks`
@@ -80,23 +79,23 @@ fn main() -> ! {
8079

8180
// The Adafruit boards have address 0x77 without closing the jumper on the back, the BME280 lib connects to 0x77 with `new_secondary`, use
8281
// `new_primary` for 0x76 if you close the jumper/solder bridge.
83-
let mut bme280 = BME280::new_secondary(i2c, Delay::new(cp.SYST, &clocks));
82+
let mut bme280 = BME280::new_secondary(i2c, cp.SYST.delay(&clocks));
8483
bme280
8584
.init()
8685
.map_err(|error| {
87-
hprintln!("Could not initialize bme280, Error: {:?}", error).unwrap();
86+
hprintln!("Could not initialize bme280, Error: {:?}", error);
8887
panic!();
8988
})
9089
.unwrap();
9190
loop {
9291
match bme280.measure() {
9392
Ok(measurements) => {
94-
hprintln!("Relative Humidity = {}%", measurements.humidity).unwrap();
95-
hprintln!("Temperature = {} deg C", measurements.temperature).unwrap();
96-
hprintln!("Pressure = {} pascals", measurements.pressure).unwrap();
93+
hprintln!("Relative Humidity = {}%", measurements.humidity);
94+
hprintln!("Temperature = {} deg C", measurements.temperature);
95+
hprintln!("Pressure = {} pascals", measurements.pressure)
9796
}
9897
Err(error) => {
99-
hprintln!("Could not read bme280 due to error: {:?}", error).unwrap();
98+
hprintln!("Could not read bme280 due to error: {:?}", error);
10099
}
101100
}
102101
}

‎src/rcc.rs‎

Lines changed: 52 additions & 52 deletions
Original file line numberDiff line numberDiff line change
@@ -495,12 +495,12 @@ impl Default for Config {
495495
Self {
496496
hse: None,
497497
pllmul: None,
498-
hpre: HPre::DIV1,
499-
ppre1: PPre::DIV1,
500-
ppre2: PPre::DIV1,
498+
hpre: HPre::Div1,
499+
ppre1: PPre::Div1,
500+
ppre2: PPre::Div1,
501501
#[cfg(any(feature = "stm32f103", feature = "connectivity"))]
502-
usbpre: UsbPre::DIV1_5,
503-
adcpre: AdcPre::DIV2,
502+
usbpre: UsbPre::Div15,
503+
adcpre: AdcPre::Div2,
504504
}
505505
}
506506
}
@@ -509,38 +509,38 @@ impl Default for Config {
509509
#[derive(Clone, Copy, Debug, PartialEq, Eq)]
510510
pub enum HPre {
511511
/// SYSCLK not divided
512-
DIV1 = 7,
512+
Div1 = 7,
513513
/// SYSCLK divided by 2
514-
DIV2 = 8,
514+
Div2 = 8,
515515
/// SYSCLK divided by 4
516-
DIV4 = 9,
516+
Div4 = 9,
517517
/// SYSCLK divided by 8
518-
DIV8 = 10,
518+
Div8 = 10,
519519
/// SYSCLK divided by 16
520-
DIV16 = 11,
520+
Div16 = 11,
521521
/// SYSCLK divided by 64
522-
DIV64 = 12,
522+
Div64 = 12,
523523
/// SYSCLK divided by 128
524-
DIV128 = 13,
524+
Div128 = 13,
525525
/// SYSCLK divided by 256
526-
DIV256 = 14,
526+
Div256 = 14,
527527
/// SYSCLK divided by 512
528-
DIV512 = 15,
528+
Div512 = 15,
529529
}
530530

531531
#[derive(Clone, Copy, Debug, PartialEq, Eq)]
532532
#[repr(u8)]
533533
pub enum PPre {
534534
/// HCLK not divided
535-
DIV1 = 3,
535+
Div1 = 3,
536536
/// HCLK divided by 2
537-
DIV2 = 4,
537+
Div2 = 4,
538538
/// HCLK divided by 4
539-
DIV4 = 5,
539+
Div4 = 5,
540540
/// HCLK divided by 8
541-
DIV8 = 6,
541+
Div8 = 6,
542542
/// HCLK divided by 16
543-
DIV16 = 7,
543+
Div16 = 7,
544544
}
545545

546546
#[cfg(feature = "stm32f103")]
@@ -582,18 +582,18 @@ impl Config {
582582

583583
let hpre_bits = if let Some(hclk) = cfgr.hclk {
584584
match sysclk / hclk {
585-
0..=1 => HPre::DIV1,
586-
2 => HPre::DIV2,
587-
3..=5 => HPre::DIV4,
588-
6..=11 => HPre::DIV8,
589-
12..=39 => HPre::DIV16,
590-
40..=95 => HPre::DIV64,
591-
96..=191 => HPre::DIV128,
592-
192..=383 => HPre::DIV256,
593-
_ => HPre::DIV512,
585+
0..=1 => HPre::Div1,
586+
2 => HPre::Div2,
587+
3..=5 => HPre::Div4,
588+
6..=11 => HPre::Div8,
589+
12..=39 => HPre::Div16,
590+
40..=95 => HPre::Div64,
591+
96..=191 => HPre::Div128,
592+
192..=383 => HPre::Div256,
593+
_ => HPre::Div512,
594594
}
595595
} else {
596-
HPre::DIV1
596+
HPre::Div1
597597
};
598598

599599
let hclk = if hpre_bits as u8 >= 0b1100 {
@@ -610,23 +610,23 @@ impl Config {
610610
36_000_000
611611
};
612612
let ppre1_bits = match (hclk + pclk1 - 1) / pclk1 {
613-
0 | 1 => PPre::DIV1,
614-
2 => PPre::DIV2,
615-
3..=5 => PPre::DIV4,
616-
6..=11 => PPre::DIV8,
617-
_ => PPre::DIV16,
613+
0 | 1 => PPre::Div1,
614+
2 => PPre::Div2,
615+
3..=5 => PPre::Div4,
616+
6..=11 => PPre::Div8,
617+
_ => PPre::Div16,
618618
};
619619

620620
let ppre2_bits = if let Some(pclk2) = cfgr.pclk2 {
621621
match hclk / pclk2 {
622-
0..=1 => PPre::DIV1,
623-
2 => PPre::DIV2,
624-
3..=5 => PPre::DIV4,
625-
6..=11 => PPre::DIV8,
626-
_ => PPre::DIV16,
622+
0..=1 => PPre::Div1,
623+
2 => PPre::Div2,
624+
3..=5 => PPre::Div4,
625+
6..=11 => PPre::Div8,
626+
_ => PPre::Div16,
627627
}
628628
} else {
629-
PPre::DIV1
629+
PPre::Div1
630630
};
631631

632632
let ppre2 = 1 << (ppre2_bits as u8 - 0b011);
@@ -635,19 +635,19 @@ impl Config {
635635
// usbpre == false: divide clock by 1.5, otherwise no division
636636
#[cfg(any(feature = "stm32f103", feature = "connectivity"))]
637637
let usbpre = match (hse, pllmul_bits, sysclk) {
638-
(Some(_), Some(_), 72_000_000) => UsbPre::DIV1_5,
639-
_ => UsbPre::DIV1,
638+
(Some(_), Some(_), 72_000_000) => UsbPre::Div15,
639+
_ => UsbPre::Div1,
640640
};
641641

642642
let apre_bits = if let Some(adcclk) = cfgr.adcclk {
643643
match pclk2 / adcclk {
644-
0..=2 => AdcPre::DIV2,
645-
3..=4 => AdcPre::DIV4,
646-
5..=7 => AdcPre::DIV6,
647-
_ => AdcPre::DIV8,
644+
0..=2 => AdcPre::Div2,
645+
3..=4 => AdcPre::Div4,
646+
5..=7 => AdcPre::Div6,
647+
_ => AdcPre::Div8,
648648
}
649649
} else {
650-
AdcPre::DIV8
650+
AdcPre::Div8
651651
};
652652

653653
Self {
@@ -731,12 +731,12 @@ fn rcc_config_usb() {
731731
let config_expected = Config {
732732
hse: Some(8_000_000),
733733
pllmul: Some(4),
734-
hpre: HPre::DIV1,
735-
ppre1: PPre::DIV2,
736-
ppre2: PPre::DIV1,
734+
hpre: HPre::Div1,
735+
ppre1: PPre::Div2,
736+
ppre2: PPre::Div1,
737737
#[cfg(any(feature = "stm32f103", feature = "connectivity"))]
738-
usbpre: UsbPre::DIV1,
739-
adcpre: AdcPre::DIV8,
738+
usbpre: UsbPre::Div1,
739+
adcpre: AdcPre::Div8,
740740
};
741741
assert_eq!(config, config_expected);
742742

‎src/serial.rs‎

Lines changed: 2 additions & 2 deletions
Original file line numberDiff line numberDiff line change
@@ -385,8 +385,8 @@ fn apply_config<USART: Instance>(config: Config, clocks: &Clocks) {
385385
});
386386
use crate::pac::usart1::cr1::PS_A;
387387
w.ps().variant(match config.parity {
388-
Parity::ParityOdd => PS_A::ODD,
389-
_ => PS_A::EVEN,
388+
Parity::ParityOdd => PS_A::Odd,
389+
_ => PS_A::Even,
390390
});
391391
w.pce().bit(!matches!(config.parity, Parity::ParityNone));
392392
w

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