Merge pull request #317 from jr-oss/fix_uart_busy_handling

Author: Sh3Rm4n

CHANGELOG.md

@@ -21,6 +21,8 @@ and this project adheres to [Semantic Versioning](http://semver.org/).
 ### Fixed
 
 - Missing `MosiPin` impl for `PB5` ([#322])
+- Read valid data from data register even if reception of next character
+  has started ([#317])
 
 ## [v0.9.0] - 2022-03-06
 
@@ -562,6 +564,7 @@ let clocks = rcc
 
 [#322]: https://github.com/stm32-rs/stm32f3xx-hal/pull/322
 [#318]: https://github.com/stm32-rs/stm32f3xx-hal/pull/318
+[#317]: https://github.com/stm32-rs/stm32f3xx-hal/pull/317
 [#314]: https://github.com/stm32-rs/stm32f3xx-hal/pull/314
 [#309]: https://github.com/stm32-rs/stm32f3xx-hal/pull/309
 [#308]: https://github.com/stm32-rs/stm32f3xx-hal/pull/308

src/adc/config.rs

@@ -50,7 +50,7 @@ use core::convert::TryFrom;
 /// [`Adc::set_pin_sequence_position`]: `super::Adc::set_pin_sequence_position`
 /// [`Adc::set_channel_sequence_position`]: `super::Adc::set_channel_sequence_position`
 /// [`Adc::channel_sequence`]: `super::Adc::channel_sequence`
-#[derive(Debug, PartialEq, PartialOrd, Copy, Clone)]
+#[derive(Debug, PartialEq, PartialOrd, Eq, Ord, Copy, Clone)]
 #[cfg_attr(feature = "defmt", derive(defmt::Format))]
 #[allow(missing_docs)]
 pub enum Sequence {

src/serial.rs

@@ -881,9 +881,7 @@ where
 {
     let isr = usart.isr.read();
 
-    Err(if isr.busy().bit_is_set() {
-        nb::Error::WouldBlock
-    } else if isr.pe().bit_is_set() {
+    Err(if isr.pe().bit_is_set() {
         usart.icr.write(|w| w.pecf().clear());
         nb::Error::Other(Error::Parity)
     } else if isr.fe().bit_is_set() {

src/serial/config.rs

@@ -6,7 +6,7 @@ use crate::time::rate::{Baud, Extensions};
 /// Stop Bit configuration parameter for serial.
 ///
 /// Wrapper around [`STOP_A`]
-#[derive(Clone, Copy, Debug, PartialEq)]
+#[derive(Clone, Copy, Debug, PartialEq, Eq)]
 #[cfg_attr(feature = "defmt", derive(defmt::Format))]
 pub enum StopBits {
     /// 0.5 stop bit
@@ -45,7 +45,7 @@ impl From<STOP_A> for StopBits {
 /// underlying USART will be configured to send/receive the parity bit in
 /// addtion to the data bits.
 #[cfg_attr(feature = "defmt", derive(defmt::Format))]
-#[derive(Debug, Clone, Copy, PartialEq)]
+#[derive(Debug, Clone, Copy, PartialEq, Eq)]
 pub enum Parity {
     /// No parity bit will be added/checked.
     None,
@@ -73,7 +73,7 @@ pub enum Parity {
 /// assert!(config.parity == Parity::None);
 /// assert!(config.stopbits == StopBits::STOP1);
 /// ```
-#[derive(Debug, Clone, Copy, PartialEq)]
+#[derive(Debug, Clone, Copy, PartialEq, Eq)]
 #[non_exhaustive]
 pub struct Config {
     /// Serial interface baud rate

src/spi/config.rs

@@ -35,7 +35,7 @@ use crate::time::rate::Generic;
 /// assert!(config.parity == Parity::None);
 /// assert!(config.stopbits == StopBits::STOP1);
 /// ```
-#[derive(Clone, Copy, PartialEq)]
+#[derive(Clone, Copy, PartialEq, Eq)]
 #[non_exhaustive]
 pub struct Config {
     /// Operating frequency of the SPI peripheral.

testsuite/tests/uart.rs

@@ -445,6 +445,30 @@ mod tests {
 
         state.serial1 = Some(serial);
     }
+
+    #[test]
+    fn test_busy_does_not_prevent_reading_data_register(state: &mut super::State) {
+        let mut serial = state.serial1.take().unwrap();
+
+        while serial.is_busy() {}
+
+        let b1 = TEST_MSG[0];
+        let b2 = TEST_MSG[1];
+
+        unwrap!(nb::block!(serial.write(b1)));
+        while !serial.is_busy() {} // Wait until reception b1 started
+        while serial.is_busy() {} // Wait until reception b1 complete
+        unwrap!(nb::block!(serial.write(b2)));
+        while !serial.is_busy() {} // Wait until reception b2 started
+
+        let c1 = unwrap!(nb::block!(serial.read())); // b1 in data register, b2 in shift register
+        let c2 = unwrap!(nb::block!(serial.read())); // wait for b2 in data register
+
+        assert_eq!(b1, c1);
+        assert_eq!(b2, c2);
+
+        state.serial1 = Some(serial);
+    }
 }
 
 // TODO: This maybe can be moved into a function inside the