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Sh3Rm4nSh3Rm4n
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Merge pull request #39 from Sh3Rm4n/update-stm32f3-2
Update stm32f3 to 0.9
2 parents 4d0c2fd + 9938d06 commit 4bbe410

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‎CHANGELOG.md‎

Lines changed: 1 addition & 0 deletions
Original file line numberDiff line numberDiff line change
@@ -24,6 +24,7 @@ and this project adheres to [Semantic Versioning](http://semver.org/).
2424
([#21](https://github.com/stm32-rs/stm32f3xx-hal/pull/21))
2525
- `stm32f303` is now split into `stm32f303xd` and `stm32f303xe` as they provide
2626
different alternate gpio functions. `stm32f303` is still available.
27+
- Bump `stm32f3` dependency to `0.9.0` ([#39](https://github.com/stm32-rs/stm32f3xx-hal/pull/39))
2728

2829
### Fixed
2930

‎Cargo.toml‎

Lines changed: 1 addition & 1 deletion
Original file line numberDiff line numberDiff line change
@@ -21,7 +21,7 @@ cortex-m = ">=0.5.8,<0.7"
2121
cortex-m-rt = "0.6.8"
2222
embedded-hal = "0.2.3"
2323
nb = "0.1.2"
24-
stm32f3 = "0.8.0"
24+
stm32f3 = "0.9.0"
2525

2626
[dependencies.bare-metal]
2727
version = "0.2.4"

‎src/i2c.rs‎

Lines changed: 20 additions & 20 deletions
Original file line numberDiff line numberDiff line change
@@ -84,15 +84,15 @@ pub struct I2c<I2C, PINS> {
8484
}
8585

8686
macro_rules! busy_wait {
87-
($i2c:expr, $flag:ident) => {
87+
($i2c:expr, $flag:ident, $variant:ident) => {
8888
loop {
8989
let isr = $i2c.isr.read();
9090

91-
if isr.berr().bit_is_set() {
91+
if isr.berr().is_error() {
9292
return Err(Error::Bus);
93-
} else if isr.arlo().bit_is_set() {
93+
} else if isr.arlo().is_lost() {
9494
return Err(Error::Arbitration);
95-
} else if isr.$flag().bit_is_set() {
95+
} else if isr.$flag().$variant() {
9696
break;
9797
} else {
9898
// try again
@@ -117,8 +117,8 @@ macro_rules! hal {
117117
SCL: SclPin<$I2CX>,
118118
SDA: SdaPin<$I2CX>,
119119
{
120-
apb1.enr().modify(|_, w| w.$i2cXen().set_bit());
121-
apb1.rstr().modify(|_, w| w.$i2cXrst().set_bit());
120+
apb1.enr().modify(|_, w| w.$i2cXen().enabled());
121+
apb1.rstr().modify(|_, w| w.$i2cXrst().reset());
122122
apb1.rstr().modify(|_, w| w.$i2cXrst().clear_bit());
123123

124124
let freq = freq.into().0;
@@ -196,7 +196,7 @@ macro_rules! hal {
196196
});
197197

198198
// Enable the peripheral
199-
i2c.cr1.write(|w| w.pe().set_bit());
199+
i2c.cr1.write(|w| w.pe().enabled());
200200

201201
I2c { i2c, pins }
202202
}
@@ -219,19 +219,19 @@ macro_rules! hal {
219219
w.sadd()
220220
.bits(u16::from(addr << 1))
221221
.rd_wrn()
222-
.clear_bit()
222+
.write()
223223
.nbytes()
224224
.bits(bytes.len() as u8)
225225
.start()
226-
.set_bit()
226+
.start()
227227
.autoend()
228-
.set_bit()
228+
.automatic()
229229
});
230230

231231
for byte in bytes {
232232
// Wait until we are allowed to send data (START has been ACKed or last byte
233233
// when through)
234-
busy_wait!(self.i2c, txis);
234+
busy_wait!(self.i2c, txis, is_empty);
235235

236236
// put byte on the wire
237237
self.i2c.txdr.write(|w| w.txdata().bits(*byte));
@@ -267,44 +267,44 @@ macro_rules! hal {
267267
w.sadd()
268268
.bits(u16::from(addr << 1))
269269
.rd_wrn()
270-
.clear_bit()
270+
.write()
271271
.nbytes()
272272
.bits(bytes.len() as u8)
273273
.start()
274-
.set_bit()
274+
.start()
275275
.autoend()
276-
.clear_bit()
276+
.software()
277277
});
278278

279279
for byte in bytes {
280280
// Wait until we are allowed to send data (START has been ACKed or last byte
281281
// when through)
282-
busy_wait!(self.i2c, txis);
282+
busy_wait!(self.i2c, txis, is_empty);
283283

284284
// put byte on the wire
285285
self.i2c.txdr.write(|w| w.txdata().bits(*byte));
286286
}
287287

288288
// Wait until the last transmission is finished
289-
busy_wait!(self.i2c, tc);
289+
busy_wait!(self.i2c, tc, is_complete);
290290

291291
// reSTART and prepare to receive bytes into `buffer`
292292
self.i2c.cr2.write(|w| {
293293
w.sadd()
294294
.bits(u16::from(addr << 1))
295295
.rd_wrn()
296-
.set_bit()
296+
.read()
297297
.nbytes()
298298
.bits(buffer.len() as u8)
299299
.start()
300-
.set_bit()
300+
.start()
301301
.autoend()
302-
.set_bit()
302+
.automatic()
303303
});
304304

305305
for byte in buffer {
306306
// Wait until we have received something
307-
busy_wait!(self.i2c, rxne);
307+
busy_wait!(self.i2c, rxne, is_not_empty);
308308

309309
*byte = self.i2c.rxdr.read().rxdata().bits();
310310
}

‎src/rcc.rs‎

Lines changed: 8 additions & 8 deletions
Original file line numberDiff line numberDiff line change
@@ -195,14 +195,14 @@ impl CFGR {
195195
feature = "stm32f303xe",
196196
feature = "stm32f398"
197197
)))]
198-
fn calc_pll(&self) -> (u32, u32, rcc::cfgr::PLLSRCW) {
198+
fn calc_pll(&self) -> (u32, u32, rcc::cfgr::PLLSRC_A) {
199199
let pllsrcclk = self.hse.unwrap_or(HSI / 2);
200200
let pllmul = self.sysclk.unwrap_or(pllsrcclk) / pllsrcclk;
201201

202202
let pllsrc = if self.hse.is_some() {
203-
rcc::cfgr::PLLSRCW::HSE_DIV_PREDIV
203+
rcc::cfgr::PLLSRC_A::HSE_DIV_PREDIV
204204
} else {
205-
rcc::cfgr::PLLSRCW::HSI_DIV2
205+
rcc::cfgr::PLLSRC_A::HSI_DIV2
206206
};
207207
(pllsrcclk, pllmul, pllsrc)
208208
}
@@ -214,24 +214,24 @@ impl CFGR {
214214
feature = "stm32f303xe",
215215
feature = "stm32f398",
216216
))]
217-
fn calc_pll(&self) -> (u32, u32, rcc::cfgr::PLLSRCW) {
217+
fn calc_pll(&self) -> (u32, u32, rcc::cfgr::PLLSRC_A) {
218218
let mut pllsrcclk = self.hse.unwrap_or(HSI / 2);
219219
let mut pllmul = self.sysclk.unwrap_or(pllsrcclk) / pllsrcclk;
220220

221221
let pllsrc = if self.hse.is_some() {
222-
rcc::cfgr::PLLSRCW::HSE_DIV_PREDIV
222+
rcc::cfgr::PLLSRC_A::HSE_DIV_PREDIV
223223
} else if pllmul > 16 {
224224
pllmul /= 2;
225225
pllsrcclk *= 2;
226-
rcc::cfgr::PLLSRCW::HSI_DIV_PREDIV
226+
rcc::cfgr::PLLSRC_A::HSI_DIV_PREDIV
227227
} else {
228-
rcc::cfgr::PLLSRCW::HSI_DIV2
228+
rcc::cfgr::PLLSRC_A::HSI_DIV2
229229
};
230230
(pllsrcclk, pllmul, pllsrc)
231231
}
232232

233233
/// Returns a tuple containing the effective sysclk rate and optional pll settings.
234-
fn calc_sysclk(&self) -> (u32, Option<(u8, rcc::cfgr::PLLSRCW)>) {
234+
fn calc_sysclk(&self) -> (u32, Option<(u8, rcc::cfgr::PLLSRC_A)>) {
235235
let (pllsrcclk, pllmul, pllsrc) = self.calc_pll();
236236
if pllmul == 1 {
237237
return (pllsrcclk, None);

‎src/spi.rs‎

Lines changed: 42 additions & 41 deletions
Original file line numberDiff line numberDiff line change
@@ -134,30 +134,15 @@ macro_rules! hal {
134134
MOSI: MosiPin<$SPIX>,
135135
{
136136
// enable or reset $SPIX
137-
apb2.enr().modify(|_, w| w.$spiXen().set_bit());
138-
apb2.rstr().modify(|_, w| w.$spiXrst().set_bit());
137+
apb2.enr().modify(|_, w| w.$spiXen().enabled());
138+
apb2.rstr().modify(|_, w| w.$spiXrst().reset());
139139
apb2.rstr().modify(|_, w| w.$spiXrst().clear_bit());
140140

141141
// FRXTH: RXNE event is generated if the FIFO level is greater than or equal to
142142
// 8-bit
143143
// DS: 8-bit data size
144144
// SSOE: Slave Select output disabled
145-
spi.cr2
146-
.write(|w| unsafe {
147-
w.frxth().set_bit().ds().bits(0b111).ssoe().clear_bit()
148-
});
149-
150-
let br = match clocks.$pclkX().0 / freq.into().0 {
151-
0 => unreachable!(),
152-
1..=2 => 0b000,
153-
3..=5 => 0b001,
154-
6..=11 => 0b010,
155-
12..=23 => 0b011,
156-
24..=39 => 0b100,
157-
40..=95 => 0b101,
158-
96..=191 => 0b110,
159-
_ => 0b111,
160-
};
145+
spi.cr2.write(|w| w.frxth().quarter().ds().eight_bit().ssoe().disabled());
161146

162147
// CPHA: phase
163148
// CPOL: polarity
@@ -170,26 +155,42 @@ macro_rules! hal {
170155
// CRCEN: hardware CRC calculation disabled
171156
// BIDIMODE: 2 line unidirectional (full duplex)
172157
spi.cr1.write(|w| {
173-
w.cpha()
174-
.bit(mode.phase == Phase::CaptureOnSecondTransition)
175-
.cpol()
176-
.bit(mode.polarity == Polarity::IdleHigh)
177-
.mstr()
178-
.set_bit()
179-
.br()
180-
.bits(br)
181-
.spe()
182-
.set_bit()
158+
w.mstr().master();
159+
160+
match mode.phase {
161+
Phase::CaptureOnFirstTransition => w.cpha().first_edge(),
162+
Phase::CaptureOnSecondTransition => w.cpha().second_edge(),
163+
};
164+
165+
match mode.polarity {
166+
Polarity::IdleLow => w.cpol().idle_low(),
167+
Polarity::IdleHigh => w.cpol().idle_high(),
168+
};
169+
170+
match clocks.$pclkX().0 / freq.into().0 {
171+
0 => unreachable!(),
172+
1..=2 => w.br().div2(),
173+
3..=5 => w.br().div4(),
174+
6..=11 => w.br().div8(),
175+
12..=23 => w.br().div16(),
176+
24..=39 => w.br().div32(),
177+
40..=95 => w.br().div64(),
178+
96..=191 => w.br().div128(),
179+
_ => w.br().div256(),
180+
};
181+
182+
w.spe()
183+
.enabled()
184+
.lsbfirst()
183185
.lsbfirst()
184-
.clear_bit()
185186
.ssi()
186-
.set_bit()
187+
.slave_not_selected()
187188
.ssm()
188-
.set_bit()
189+
.enabled()
189190
.crcen()
190-
.clear_bit()
191+
.disabled()
191192
.bidimode()
192-
.clear_bit()
193+
.unidirectional()
193194
});
194195

195196
Spi { spi, pins }
@@ -207,13 +208,13 @@ macro_rules! hal {
207208
fn read(&mut self) -> nb::Result<u8, Error> {
208209
let sr = self.spi.sr.read();
209210

210-
Err(if sr.ovr().bit_is_set() {
211+
Err(if sr.ovr().is_overrun() {
211212
nb::Error::Other(Error::Overrun)
212-
} else if sr.modf().bit_is_set() {
213+
} else if sr.modf().is_fault() {
213214
nb::Error::Other(Error::ModeFault)
214-
} else if sr.crcerr().bit_is_set() {
215+
} else if sr.crcerr().is_no_match() {
215216
nb::Error::Other(Error::Crc)
216-
} else if sr.rxne().bit_is_set() {
217+
} else if sr.rxne().is_not_empty() {
217218
// NOTE(read_volatile) read only 1 byte (the svd2rust API only allows
218219
// reading a half-word)
219220
return Ok(unsafe {
@@ -227,13 +228,13 @@ macro_rules! hal {
227228
fn send(&mut self, byte: u8) -> nb::Result<(), Error> {
228229
let sr = self.spi.sr.read();
229230

230-
Err(if sr.ovr().bit_is_set() {
231+
Err(if sr.ovr().is_overrun() {
231232
nb::Error::Other(Error::Overrun)
232-
} else if sr.modf().bit_is_set() {
233+
} else if sr.modf().is_fault() {
233234
nb::Error::Other(Error::ModeFault)
234-
} else if sr.crcerr().bit_is_set() {
235+
} else if sr.crcerr().is_no_match() {
235236
nb::Error::Other(Error::Crc)
236-
} else if sr.txe().bit_is_set() {
237+
} else if sr.txe().is_empty() {
237238
// NOTE(write_volatile) see note above
238239
unsafe { ptr::write_volatile(&self.spi.dr as *const _ as *mut u8, byte) }
239240
return Ok(());

‎src/timer.rs‎

Lines changed: 11 additions & 9 deletions
Original file line numberDiff line numberDiff line change
@@ -112,21 +112,23 @@ macro_rules! hal {
112112

113113
let arr = u16(ticks / u32(psc + 1)).unwrap();
114114

115+
// TODO (sh3rm4n)
116+
// self.tim.arr.write(|w| { w.arr().bits(arr) });
115117
self.tim.arr.write(|w| unsafe { w.bits(u32(arr)) });
116118

117119
// Trigger an update event to load the prescaler value to the clock
118-
self.tim.egr.write(|w| w.ug().set_bit());
120+
self.tim.egr.write(|w| w.ug().update());
119121
// The above line raises an update event which will indicate
120122
// that the timer is already finished. Since this is not the case,
121123
// it should be cleared
122124
self.clear_update_interrupt_flag();
123125

124126
// start counter
125-
self.tim.cr1.modify(|_, w| w.cen().set_bit());
127+
self.tim.cr1.modify(|_, w| w.cen().enabled());
126128
}
127129

128130
fn wait(&mut self) -> nb::Result<(), Void> {
129-
if self.tim.sr.read().uif().bit_is_clear() {
131+
if self.tim.sr.read().uif().is_clear() {
130132
Err(nb::Error::WouldBlock)
131133
} else {
132134
self.clear_update_interrupt_flag();
@@ -142,8 +144,8 @@ macro_rules! hal {
142144
T: Into<Hertz>,
143145
{
144146
// enable and reset peripheral to a clean slate state
145-
$apb.enr().modify(|_, w| w.$timXen().set_bit());
146-
$apb.rstr().modify(|_, w| w.$timXrst().set_bit());
147+
$apb.enr().modify(|_, w| w.$timXen().enabled());
148+
$apb.rstr().modify(|_, w| w.$timXrst().reset());
147149
$apb.rstr().modify(|_, w| w.$timXrst().clear_bit());
148150

149151
let mut timer = Timer { clocks, tim };
@@ -155,25 +157,25 @@ macro_rules! hal {
155157
/// Starts listening for an `event`
156158
pub fn listen(&mut self, event: Event) {
157159
match event {
158-
Event::Update => self.tim.dier.write(|w| w.uie().set_bit()),
160+
Event::Update => self.tim.dier.write(|w| w.uie().enabled()),
159161
}
160162
}
161163

162164
/// Stops listening for an `event`
163165
pub fn unlisten(&mut self, event: Event) {
164166
match event {
165-
Event::Update => self.tim.dier.write(|w| w.uie().clear_bit()),
167+
Event::Update => self.tim.dier.write(|w| w.uie().disabled()),
166168
}
167169
}
168170

169171
/// Stops the timer
170172
pub fn stop(&mut self) {
171-
self.tim.cr1.modify(|_, w| w.cen().clear_bit());
173+
self.tim.cr1.modify(|_, w| w.cen().disabled());
172174
}
173175

174176
/// Clears Update Interrupt Flag
175177
pub fn clear_update_interrupt_flag(&mut self) {
176-
self.tim.sr.modify(|_, w| w.uif().clear_bit());
178+
self.tim.sr.modify(|_, w| w.uif().clear());
177179
}
178180

179181
/// Releases the TIM peripheral

‎src/usb.rs‎

Lines changed: 2 additions & 2 deletions
Original file line numberDiff line numberDiff line change
@@ -34,10 +34,10 @@ unsafe impl UsbPeripheral for Peripheral {
3434

3535
cortex_m::interrupt::free(|_| {
3636
// Enable USB peripheral
37-
rcc.apb1enr.modify(|_, w| w.usben().set_bit());
37+
rcc.apb1enr.modify(|_, w| w.usben().enabled());
3838

3939
// Reset USB peripheral
40-
rcc.apb1rstr.modify(|_, w| w.usbrst().set_bit());
40+
rcc.apb1rstr.modify(|_, w| w.usbrst().reset());
4141
rcc.apb1rstr.modify(|_, w| w.usbrst().clear_bit());
4242
});
4343
}

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