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Add serial test for read write methods and different baud rates
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testsuite/tests/uart.rs

Lines changed: 44 additions & 34 deletions
Original file line numberDiff line numberDiff line change
@@ -1,19 +1,21 @@
11
#![no_std]
22
#![no_main]
33

4-
// TODO: Get pa9 and pa10 because these also implement spi and uart
54
use testsuite as _;
65

76
use stm32f3xx_hal as hal;
87

9-
use hal::gpio::{
10-
gpioa::{PA10, PA2, PA3, PA9},
11-
gpiob::{PB10, PB11},
12-
};
138
use hal::gpio::{OpenDrain, PushPull, AF7};
149
use hal::pac;
1510
use hal::prelude::*;
16-
use hal::serial::{Rx, Serial, Tx};
11+
use hal::serial::Serial;
12+
use hal::{
13+
gpio::{
14+
gpioa::{PA10, PA2, PA3, PA9},
15+
gpiob::{PB10, PB11},
16+
},
17+
rcc::{Clocks, APB2},
18+
};
1719

1820
use core::array::IntoIter;
1921

@@ -23,6 +25,8 @@ struct State {
2325
serial1: Option<Serial<pac::USART1, (PA9<AF7<PushPull>>, PA10<AF7<PushPull>>)>>,
2426
serial_slow: Option<Serial<pac::USART2, (PA2<AF7<PushPull>>, PA3<AF7<OpenDrain>>)>>,
2527
serial_fast: Option<Serial<pac::USART3, (PB10<AF7<PushPull>>, PB11<AF7<OpenDrain>>)>>,
28+
clocks: Clocks,
29+
apb2: APB2,
2630
}
2731

2832
const TEST_MSG: [u8; 8] = [0xD, 0xE, 0xA, 0xD, 0xB, 0xE, 0xE, 0xF];
@@ -31,7 +35,7 @@ const TEST_MSG: [u8; 8] = [0xD, 0xE, 0xA, 0xD, 0xB, 0xE, 0xE, 0xF];
3135
mod tests {
3236
use super::*;
3337
use defmt::{self, assert, assert_eq, unwrap};
34-
use testsuite::{SerialPair, CrossSerialPair1, CrossSerialPair2};
38+
use testsuite::{CrossSerialPair1, CrossSerialPair2, SerialPair};
3539

3640
#[init]
3741
fn init() -> super::State {
@@ -90,36 +94,34 @@ mod tests {
9094
clocks,
9195
&mut rcc.apb1,
9296
)),
97+
clocks,
98+
apb2: rcc.apb2,
9399
}
94-
95-
// super::State { serial, clocks, apb2: rcc.apb2 }
96100
}
97101

98-
// Problems:
99-
// 1. if we split, we can not join (no runtime informatino which pins where associated with the
100-
// uart)
101-
// 2. if we free, we could crate a new one,
102-
// 3. but to use the serial we **have** to split, so this is useless
103-
// 4. So we have to implement join and than split on the whole uart to gain the uart + pins again.
104-
// 5. We should introduce the builder pattern (config pattern instead of dirtctl setting the
105-
// buad rate)
106-
// 6. No way to set parity etc.
107-
// 7. We have to implement read and write directly on the peripheral
108-
// - Maybe this should also follow
109-
//
110-
// #[test]
111-
// fn send_receive_split_fast(state: &mut super::State) {
112-
// let (usart, pins) = unwrap!(state.serial1.take()).free();
113-
// let mut serial = Serial::usart1(usart, pins, 115200.Bd(), state.clocks, &mut state.apb2);
114-
// let (mut tx, mut rx) = serial.split();
115-
// for i in &TEST_MSG {
116-
// nb::block!(tx.write(*i));
117-
// let c = unwrap!(nb::block!(rx.read()));
118-
// assert_eq!(c, *i);
119-
// }
120-
121-
// state.serial = Some(serial);
122-
// }
102+
#[test]
103+
fn test_many_baudrates(state: &mut super::State) {
104+
use hal::time::rate::Baud;
105+
for baudrate in &[
106+
Baud(1200),
107+
Baud(9600),
108+
Baud(19200),
109+
Baud(38400),
110+
Baud(57600),
111+
Baud(115200),
112+
Baud(230400),
113+
Baud(460800),
114+
] {
115+
let (usart, pins) = unwrap!(state.serial1.take()).free();
116+
let mut serial = Serial::usart1(usart, pins, *baudrate, state.clocks, &mut state.apb2);
117+
for i in &TEST_MSG {
118+
unwrap!(nb::block!(serial.write(*i)));
119+
let c = unwrap!(nb::block!(serial.read()));
120+
assert_eq!(c, *i);
121+
}
122+
state.serial1 = Some(serial);
123+
}
124+
}
123125

124126
#[test]
125127
fn send_receive_split(state: &mut super::State) {
@@ -156,4 +158,12 @@ mod tests {
156158
defmt::info!("{}", c);
157159
assert!(matches!(c, Err(Error::Framing)));
158160
}
161+
162+
// TODO: Check the parity. But currently, there is no way to configure the parity
163+
// #[test]
164+
// fn check_parity(state: &mut super::State) { }
165+
166+
// TODO: Test interrupts
167+
// #[test]
168+
// fn enable_interrupt_and_wait_for_fire(state: &mut super::State) {}
159169
}

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