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2 parents 231c959 + 1810b4b commit ff65124Copy full SHA for ff65124
src/adc.rs
@@ -399,8 +399,15 @@ macro_rules! adc_hal {
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}
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fn wait_adc_clk_cycles(&self, cycles: u32) {
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- let adc_clk_cycle = self.clocks.hclk().0 / (self.ckmode as u32);
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- asm::delay(adc_clk_cycle * cycles);
+ // using a match statement here so compilation will fail once asynchronous clk
+ // mode is implemented (CKMODE[1:0] = 00b). This will force whoever is working
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+ // on it to rethink what needs to be done here :)
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+ let adc_per_cpu_cycles = match self.ckmode {
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+ CkMode::SYNCDIV1 => 1,
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+ CkMode::SYNCDIV2 => 2,
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+ CkMode::SYNCDIV4 => 4,
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+ };
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+ asm::delay(adc_per_cpu_cycles * cycles);
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fn advregen_enable(&mut self){
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