Merge pull request #64 from stm32-rs/feature/pwr

Power controller refactoring

Author: andresv

examples/rtic_low_power.rs

@@ -0,0 +1,53 @@
+#![no_std]
+#![no_main]
+#![deny(warnings)]
+
+extern crate cortex_m;
+extern crate cortex_m_rt as rt;
+extern crate panic_semihosting;
+extern crate rtic;
+extern crate stm32g0xx_hal as hal;
+
+use hal::exti::Event;
+use hal::gpio::gpioa::PA5;
+use hal::gpio::{Output, PushPull, SignalEdge};
+use hal::power::{LowPowerMode, PowerMode};
+use hal::prelude::*;
+use hal::rcc::{self, Prescaler};
+use hal::stm32;
+use rtic::app;
+
+#[app(device = hal::stm32, peripherals = true)]
+const APP: () = {
+    struct Resources {
+        exti: stm32::EXTI,
+        led: PA5<Output<PushPull>>,
+    }
+
+    #[init]
+    fn init(mut ctx: init::Context) -> init::LateResources {
+        let mut rcc = ctx.device.RCC.freeze(rcc::Config::hsi(Prescaler::Div16));
+        let mut exti = ctx.device.EXTI;
+
+        let gpioa = ctx.device.GPIOA.split(&mut rcc);
+        let gpioc = ctx.device.GPIOC.split(&mut rcc);
+
+        let led = gpioa.pa5.into_push_pull_output();
+        let button = gpioc.pc13.listen(SignalEdge::Falling, &mut exti);
+
+        let mut power = ctx.device.PWR.constrain(&mut rcc);
+        power.set_mode(PowerMode::LowPower(LowPowerMode::StopMode2));
+
+        if button.is_high().unwrap() {
+            ctx.core.SCB.set_sleepdeep();
+        }
+
+        init::LateResources { exti, led }
+    }
+
+    #[task(binds = EXTI4_15, resources = [exti, led])]
+    fn button_click(ctx: button_click::Context) {
+        ctx.resources.led.toggle().unwrap();
+        ctx.resources.exti.unpend(Event::GPIO13);
+    }
+};

src/analog/adc.rs

@@ -116,7 +116,8 @@ pub struct CalibrationFactor(pub u8);
 impl Adc {
     pub fn new(adc: ADC, rcc: &mut Rcc) -> Self {
         // Enable ADC clocks
-        rcc.rb.apbenr2.modify(|_, w| w.adcen().set_bit());
+        rcc.enable_adc();
+
         adc.cr.modify(|_, w| w.advregen().set_bit());
 
         Self {

src/crc.rs

@@ -31,11 +31,7 @@ pub trait CrcExt {
 
 impl CrcExt for CRC {
     fn constrain(self, rcc: &mut Rcc) -> Config {
-        // Enable power to CRC unit
-        rcc.rb.ahbenr.modify(|_, w| w.crcen().set_bit());
-        // Reset CRC unit
-        rcc.rb.ahbrstr.modify(|_, w| w.crcrst().set_bit());
-        rcc.rb.ahbrstr.modify(|_, w| w.crcrst().clear_bit());
+        rcc.enable_crc();
 
         // Default values
         Config {

src/flash/mod.rs

@@ -189,7 +189,7 @@ impl WriteErase for UnlockedFlash {
 
         let mut chunks = aligned_data.chunks_exact(mem::size_of::<Self::NativeType>());
 
-        while let Some(exact_chunk) = chunks.next() {
+        for exact_chunk in &mut chunks {
             // Write chunks
             let native = &[Self::NativeType::from_ne_bytes(
                 exact_chunk.try_into().unwrap(),

src/gpio.rs

@@ -177,30 +177,35 @@ macro_rules! gpio {
                     _mode: PhantomData<MODE>,
                 }
 
+                #[allow(clippy::from_over_into)]
                 impl Into<$PXi<Input<PullDown>>> for $PXi<DefaultMode> {
                     fn into(self) -> $PXi<Input<PullDown>> {
                         self.into_pull_down_input()
                     }
                 }
 
+                #[allow(clippy::from_over_into)]
                 impl Into<$PXi<Input<PullUp>>> for $PXi<DefaultMode> {
                     fn into(self) -> $PXi<Input<PullUp>> {
                         self.into_pull_up_input()
                     }
                 }
 
+                #[allow(clippy::from_over_into)]
                 impl Into<$PXi<Input<Floating>>> for $PXi<DefaultMode> {
                     fn into(self) -> $PXi<Input<Floating>> {
                         self.into_floating_input()
                     }
                 }
 
+                #[allow(clippy::from_over_into)]
                 impl Into<$PXi<Output<OpenDrain>>> for $PXi<DefaultMode> {
                     fn into(self) -> $PXi<Output<OpenDrain>> {
                         self.into_open_drain_output()
                     }
                 }
 
+                #[allow(clippy::from_over_into)]
                 impl Into<$PXi<Output<PushPull>>> for $PXi<DefaultMode> {
                     fn into(self) -> $PXi<Output<PushPull>> {
                         self.into_push_pull_output()

src/lib.rs

@@ -53,6 +53,7 @@ pub mod exti;
 pub mod flash;
 pub mod gpio;
 pub mod i2c;
+pub mod power;
 pub mod prelude;
 pub mod rcc;
 #[cfg(any(feature = "stm32g041", feature = "stm32g081"))]

src/power.rs

@@ -0,0 +1,52 @@
+//! Power control
+
+use crate::{rcc::Rcc, stm32::PWR};
+
+pub enum LowPowerMode {
+    StopMode1 = 0b00,
+    StopMode2 = 0b01,
+    Standby = 0b11,
+}
+
+pub enum PowerMode {
+    Run,
+    LowPower(LowPowerMode),
+}
+
+pub struct Power {
+    rb: PWR,
+}
+
+impl Power {
+    pub fn new(pwr: PWR, rcc: &mut Rcc) -> Self {
+        rcc.enable_power_control();
+        Self { rb: pwr }
+    }
+
+    pub fn set_mode(&mut self, mode: PowerMode) {
+        match mode {
+            PowerMode::Run => {
+                self.rb.cr1.modify(|_, w| w.lpr().clear_bit());
+                while !self.rb.sr2.read().reglpf().bit_is_clear() {}
+            }
+            PowerMode::LowPower(sm) => {
+                self.rb
+                    .cr1
+                    .modify(|_, w| unsafe { w.lpr().set_bit().lpms().bits(sm as u8) });
+                while !self.rb.sr2.read().reglps().bit_is_set()
+                    || !self.rb.sr2.read().reglpf().bit_is_set()
+                {}
+            }
+        }
+    }
+}
+
+pub trait PowerExt {
+    fn constrain(self, rcc: &mut Rcc) -> Power;
+}
+
+impl PowerExt for PWR {
+    fn constrain(self, rcc: &mut Rcc) -> Power {
+        Power::new(self, rcc)
+    }
+}

src/prelude.rs

@@ -25,6 +25,7 @@ pub use crate::exti::ExtiExt as _;
 pub use crate::flash::FlashExt as _;
 pub use crate::gpio::GpioExt as _;
 pub use crate::i2c::I2cExt as _;
+pub use crate::power::PowerExt as _;
 pub use crate::rcc::LSCOExt as _;
 pub use crate::rcc::MCOExt as _;
 pub use crate::rcc::RccExt as _;

src/rcc/mod.rs

@@ -192,19 +192,6 @@ impl Rcc {
         }
     }
 
-    pub fn enable_low_power_mode(&self) {
-        assert!(self.clocks.sys_clk.0 <= 2_000_000);
-        self.rb.apbenr1.modify(|_, w| w.pwren().set_bit());
-        let pwr = unsafe { &(*PWR::ptr()) };
-        pwr.cr1.modify(|_, w| w.lpr().set_bit());
-    }
-
-    pub fn disable_low_power_mode(&self) {
-        self.rb.apbenr1.modify(|_, w| w.pwren().set_bit());
-        let pwr = unsafe { &(*PWR::ptr()) };
-        pwr.cr1.modify(|_, w| w.lpr().clear_bit());
-    }
-
     fn config_pll(&self, pll_cfg: PllConfig) -> PLLClocks {
         assert!(pll_cfg.m > 0 && pll_cfg.m <= 8);
         assert!(pll_cfg.r > 1 && pll_cfg.r <= 8);
@@ -324,6 +311,20 @@ impl Rcc {
                 .clear_bit()
         });
     }
+
+    pub(crate) fn enable_power_control(&self) {
+        self.rb.apbenr1.modify(|_, w| w.pwren().set_bit());
+    }
+
+    pub(crate) fn enable_adc(&self) {
+        self.rb.apbenr2.modify(|_, w| w.adcen().set_bit());
+    }
+
+    pub(crate) fn enable_crc(&self) {
+        self.rb.ahbenr.modify(|_, w| w.crcen().set_bit());
+        self.rb.ahbrstr.modify(|_, w| w.crcrst().set_bit());
+        self.rb.ahbrstr.modify(|_, w| w.crcrst().clear_bit());
+    }
 }
 
 /// Extension trait that constrains the `RCC` peripheral

src/serial/usart.rs

@@ -326,7 +326,6 @@ macro_rules! uart_shared {
                 });
             }
         }
-
     }
 }