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oldsheep68oldsheep68
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Revert "Revert "cargo fmt run""
This reverts commit 5039814.
1 parent 5039814 commit 3732abe

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2 files changed

+67
-79
lines changed

2 files changed

+67
-79
lines changed

‎examples/adc_ext_trig_double_dma_serial.rs

Lines changed: 32 additions & 38 deletions
Original file line numberDiff line numberDiff line change
@@ -9,31 +9,28 @@
99

1010
extern crate cortex_m;
1111
extern crate cortex_m_rt as rt;
12-
use cortex_m_semihosting::{ hprintln};
12+
use cortex_m_semihosting::hprintln;
1313

1414
extern crate nb;
1515
extern crate panic_halt;
16-
extern crate stm32g0xx_hal as hal;
1716
extern crate stm32g0;
18-
17+
extern crate stm32g0xx_hal as hal;
1918

2019
use hal::prelude::*;
21-
use hal::stm32;
2220
use hal::serial::*;
21+
use hal::stm32;
2322
use rt::entry;
2423

25-
use core::cell::{RefCell};
26-
use cortex_m::{ interrupt::Mutex};
24+
use core::cell::RefCell;
25+
use cortex_m::interrupt::Mutex;
2726

28-
use crate::hal::{
29-
stm32::{interrupt, Interrupt},
30-
};
31-
use hal::analog::adc::{Precision, SampleTime, InjTrigSource}; //, VTemp
27+
use crate::hal::stm32::{interrupt, Interrupt};
28+
use hal::analog::adc::{InjTrigSource, Precision, SampleTime}; //, VTemp
3229

3330
use hal::dma::{self, Channel, Target};
3431

35-
use crate::hal::analog::adc::InjectMode;
3632
use crate::hal::analog::adc::DmaMode;
33+
use crate::hal::analog::adc::InjectMode;
3734

3835
// Make dma globally available
3936
static G_DMA: Mutex<RefCell<Option<hal::dma::Channels>>> = Mutex::new(RefCell::new(None));
@@ -60,13 +57,12 @@ fn DMA_CHANNEL1() {
6057
G_DMA_BUFFER_ADDR.borrow(cs).replace(None).unwrap()
6158
})
6259
});
63-
60+
6461
let tx_dma_buf_first_addr: u32 = *dma_buf_addr;
65-
let tx_dma_buf_second_addr: u32 = *dma_buf_addr + (BUFFER_SIZE) as u32;
66-
// Address is in byte, value in 2Bytes, this is why second dma buffer ist added with BUFFER_SIZE
62+
let tx_dma_buf_second_addr: u32 = *dma_buf_addr + (BUFFER_SIZE) as u32;
63+
// Address is in byte, value in 2Bytes, this is why second dma buffer ist added with BUFFER_SIZE
6764
// and not BUFFER_SIZE/2
68-
69-
65+
7066
unsafe {
7167
let dma = &(*stm32g0::stm32g031::DMA::ptr());
7268
let htif1 = dma.isr.read().htif1().bit();
@@ -100,17 +96,16 @@ fn main() -> ! {
10096
let usart1 = dp
10197
.USART1
10298
.usart(
103-
gpioa.pa9, // TX: pa9, => CN3 Pin-D5
104-
gpioa.pa10, // RX: pa10, => CN3 Pin-D4
105-
FullConfig::default().baudrate(460800.bps())
106-
.fifo_enable(), // enable fifo, so that dma can fill it fast, otherwise it may not finish before ch1 is requested again
99+
gpioa.pa9, // TX: pa9, => CN3 Pin-D5
100+
gpioa.pa10, // RX: pa10, => CN3 Pin-D4
101+
FullConfig::default().baudrate(460800.bps()).fifo_enable(), // enable fifo, so that dma can fill it fast, otherwise it may not finish before ch1 is requested again
107102
&mut rcc,
108103
)
109104
.unwrap();
110105

111106
// DMA example
112107
//==================================================
113-
let adc_buffer1: [u16; BUFFER_SIZE as usize] = [0;BUFFER_SIZE as usize];
108+
let adc_buffer1: [u16; BUFFER_SIZE as usize] = [0; BUFFER_SIZE as usize];
114109

115110
let mut dma = dp.DMA.split(&mut rcc, dp.DMAMUX);
116111

@@ -122,16 +117,18 @@ fn main() -> ! {
122117
dma.ch1.set_word_size(dma::WordSize::BITS16);
123118
dma.ch1.set_direction(dma::Direction::FromPeripheral);
124119
dma.ch1.set_memory_address(adc_buffer1_addr, true);
125-
dma.ch1.set_peripheral_address(adc_data_register_addr, false);
120+
dma.ch1
121+
.set_peripheral_address(adc_data_register_addr, false);
126122
dma.ch1.set_transfer_length(adc_buffer1.len() as u16);
127-
123+
128124
hprintln!("adc_data_register_addr {:?}", adc_buffer1_addr).unwrap(); // will output addr in dec
129-
// in gdb read the data bytes with: x /32xh 0x??????? (last is addr in hex)
130-
// or put addr in dec format: x /32xh 536878092
131-
// https://sourceware.org/gdb/current/onlinedocs/gdb/Memory.html
125+
// in gdb read the data bytes with: x /32xh 0x??????? (last is addr in hex)
126+
// or put addr in dec format: x /32xh 536878092
127+
// https://sourceware.org/gdb/current/onlinedocs/gdb/Memory.html
132128

133129
// dma ch1 reads from ADC register into memory
134-
dma.ch1.select_peripheral(stm32g0xx_hal::dmamux::DmaMuxIndex::ADC);
130+
dma.ch1
131+
.select_peripheral(stm32g0xx_hal::dmamux::DmaMuxIndex::ADC);
135132
// The dma continuesly fills the buffer, when its full, it starts over again
136133
dma.ch1.set_circular_mode(true);
137134

@@ -156,9 +153,9 @@ fn main() -> ! {
156153
dma.ch1.enable();
157154

158155
cortex_m::interrupt::free(|cs| *G_DMA.borrow(cs).borrow_mut() = Some(dma));
159-
cortex_m::interrupt::free(|cs| *G_DMA_BUFFER_ADDR.borrow(cs).borrow_mut() = Some(adc_buffer1_addr));
160-
161-
156+
cortex_m::interrupt::free(|cs| {
157+
*G_DMA_BUFFER_ADDR.borrow(cs).borrow_mut() = Some(adc_buffer1_addr)
158+
});
162159

163160
//==================================================
164161
// Set up adc
@@ -177,26 +174,25 @@ fn main() -> ! {
177174
adc.prepare_injected(&mut pa3, InjTrigSource::TRG_2);
178175
adc.start_injected();
179176

180-
181177
// Enable timer to trigger external sources in mms value of cr2
182178
// 011: Compare Pulse - The trigger output send a positive pulse when the CC1IF flag is to be
183179
// set (even if it was already high), as soon as a capture or a compare match occurred.
184180
// ouput is (TRGO)
185181
// according to reference manual chapter 22.4.2
186182
// this is only available on timer TIM2, TIM3, TIM4 and TIM1
187-
unsafe{
183+
unsafe {
188184
// get pointer of timer 2
189185
let tim = &(*stm32g0::stm32g031::TIM2::ptr());
190-
//
191-
tim.cr2.modify(|_,w| w.mms().bits(3 as u8));
186+
//
187+
tim.cr2.modify(|_, w| w.mms().bits(3 as u8));
192188
}
193189

194190
// enable dma to be called, when adc is ready to read
195191
adc.dma_enable(true);
196192
adc.dma_circualr_mode(true);
197193

198194
// don't enabel the timer bevor the dma
199-
// Set up a timer expiring after
195+
// Set up a timer expiring after
200196
timer.start(50.us());
201197
timer.listen();
202198

@@ -205,7 +201,5 @@ fn main() -> ! {
205201
cortex_m::peripheral::NVIC::unmask(Interrupt::DMA_CHANNEL1);
206202
}
207203

208-
loop {
209-
210-
}
204+
loop {}
211205
}

‎src/analog/adc.rs

Lines changed: 35 additions & 41 deletions
Original file line numberDiff line numberDiff line change
@@ -75,17 +75,16 @@ pub enum AsyncClockDiv {
7575
/// ADC injected trigger source selection
7676
#[derive(Copy, Clone, PartialEq)]
7777
pub enum InjTrigSource {
78-
TRG_0 = 0b000, // TIM1_TRGO2
79-
TRG_1 = 0b001, // TIM1_CC4
80-
TRG_2 = 0b010, // TIM2_TRGO
81-
TRG_3 = 0b011, // TIM3_TRGO
82-
TRG_4 = 0b100, // TIM15_TRGO
83-
TRG_5 = 0b101, // TIM6_TRGO
84-
TRG_6 = 0b110, // TIM4_TRGO
85-
TRG_7 = 0b111, // EXTI11
78+
TRG_0 = 0b000, // TIM1_TRGO2
79+
TRG_1 = 0b001, // TIM1_CC4
80+
TRG_2 = 0b010, // TIM2_TRGO
81+
TRG_3 = 0b011, // TIM3_TRGO
82+
TRG_4 = 0b100, // TIM15_TRGO
83+
TRG_5 = 0b101, // TIM6_TRGO
84+
TRG_6 = 0b110, // TIM4_TRGO
85+
TRG_7 = 0b111, // EXTI11
8686
}
8787

88-
8988
/// Analog to Digital converter interface
9089
pub struct Adc {
9190
rb: ADC,
@@ -194,8 +193,10 @@ impl Adc {
194193
}
195194

196195
/// The nuber of bits, the oversampling result is shifted in bits at the end of oversampling
197-
pub fn set_oversamling_shift(&mut self, nrbits:u8) {
198-
self.rb.cfgr2.modify(|_, w| unsafe {w.ovss().bits(nrbits)});
196+
pub fn set_oversamling_shift(&mut self, nrbits: u8) {
197+
self.rb
198+
.cfgr2
199+
.modify(|_, w| unsafe { w.ovss().bits(nrbits) });
199200
}
200201

201202
/// Oversampling of adc according to datasheet of stm32g0, when oversampling is enabled
@@ -208,25 +209,27 @@ impl Adc {
208209
/// 110: 128x
209210
/// 111: 256x
210211
211-
pub fn set_oversamling_ratio(&mut self, multyply:u8) {
212-
self.rb.cfgr2.modify(|_, w| unsafe {w.ovsr().bits(multyply)});
212+
pub fn set_oversamling_ratio(&mut self, multyply: u8) {
213+
self.rb
214+
.cfgr2
215+
.modify(|_, w| unsafe { w.ovsr().bits(multyply) });
213216
}
214217

215218
pub fn oversamling_enable(&mut self) {
216-
self.rb.cfgr2.modify(|_, w| unsafe {w.ovse().set_bit()});
219+
self.rb.cfgr2.modify(|_, w| unsafe { w.ovse().set_bit() });
217220
}
218221

219222
pub fn start_injected(&mut self) {
220-
self.rb.cr.modify(|_,w| w.adstart().set_bit());
223+
self.rb.cr.modify(|_, w| w.adstart().set_bit());
221224
// ADSTART bit is cleared to 0 bevor using this function
222225
// enable self.rb.isr.eos() flag is set after each converstion
223226
self.rb.ier.modify(|_, w| w.eocie().set_bit()); // end of sequence interupt enable
224227
}
225228

226-
227-
pub fn stop_injected(&mut self) { // ?????? or is it reset after each conversion?
229+
pub fn stop_injected(&mut self) {
230+
// ?????? or is it reset after each conversion?
228231
// ADSTART bit is cleared to 0 bevor using this function
229-
// disable EOS interrupt
232+
// disable EOS interrupt
230233
// maybe self.rb.cr.adstp().set_bit() must be performed before interrupt is disabled + wait abortion
231234
self.rb.ier.modify(|_, w| w.eocie().clear_bit()); // end of sequence interupt disable
232235
}
@@ -255,39 +258,32 @@ where
255258
{
256259
type Error = ();
257260

258-
fn prepare_injected(&mut self, _pin: &mut PIN, triger_source: InjTrigSource){
259-
// set the clock mode to synchronous one
261+
fn prepare_injected(&mut self, _pin: &mut PIN, triger_source: InjTrigSource) {
262+
// set the clock mode to synchronous one
260263
// self.rb.cfgr2.ckmode().bits(CLCOKMODE) // CLOCKMODE = 01 or 10 for PCLK/2 or PCLK/4
261264

262-
263265
// self.set_injected_trigger_source(triger_source as InjTrigSource);
264-
self.rb.cfgr1.modify(|_, w| unsafe {
265-
w.exten()
266-
.bits(1)
267-
.extsel()
268-
.bits(triger_source as u8)
269-
});
266+
self.rb
267+
.cfgr1
268+
.modify(|_, w| unsafe { w.exten().bits(1).extsel().bits(triger_source as u8) });
270269

271270
self.rb.cfgr1.modify(|_, w| unsafe {
272-
w.res() // set ADC resolution bits (ADEN must be =0)
271+
w.res() // set ADC resolution bits (ADEN must be =0)
273272
.bits(self.precision as u8)
274-
.align() // set alignment bit is (ADSTART must be 0)
273+
.align() // set alignment bit is (ADSTART must be 0)
275274
.bit(self.align == Align::Left)
276275
});
277276

278277
self.power_up();
279278

280279
self.rb
281-
.smpr // set sampling time set 1 (ADSTART must be 0)
280+
.smpr // set sampling time set 1 (ADSTART must be 0)
282281
.modify(|_, w| unsafe { w.smp1().bits(self.sample_time as u8) });
283282

284283
self.rb
285-
.chselr() // set activ channel acording chapter 15.12.9 (ADC_CFGR1; CHSELRMOD=0)
284+
.chselr() // set activ channel acording chapter 15.12.9 (ADC_CFGR1; CHSELRMOD=0)
286285
.modify(|_, w| unsafe { w.chsel().bits(1 << PIN::channel()) });
287-
288286
}
289-
290-
291287
}
292288

293289
pub trait DmaMode<ADC> {
@@ -298,27 +294,25 @@ pub trait DmaMode<ADC> {
298294
}
299295

300296
impl DmaMode<Adc> for Adc {
301-
302297
type Error = ();
303298

304299
fn dma_enable(&mut self, enable: bool) {
305300
if enable {
306-
self.rb.cfgr1.modify(|_,w| w.dmaen().set_bit()); // enable dma beeing called
301+
self.rb.cfgr1.modify(|_, w| w.dmaen().set_bit()); // enable dma beeing called
307302
} else {
308-
self.rb.cfgr1.modify(|_,w| w.dmaen().clear_bit()); // disable dma beeing called
303+
self.rb.cfgr1.modify(|_, w| w.dmaen().clear_bit()); // disable dma beeing called
309304
}
310305
}
311-
306+
312307
fn dma_circualr_mode(&mut self, enable: bool) {
313308
if enable {
314-
self.rb.cfgr1.modify(|_,w| w.dmacfg().set_bit()); // activate circular mode
309+
self.rb.cfgr1.modify(|_, w| w.dmacfg().set_bit()); // activate circular mode
315310
} else {
316-
self.rb.cfgr1.modify(|_,w| w.dmacfg().clear_bit()); // disable circular mode
311+
self.rb.cfgr1.modify(|_, w| w.dmacfg().clear_bit()); // disable circular mode
317312
}
318313
}
319314
}
320315

321-
322316
impl<WORD, PIN> OneShot<Adc, WORD, PIN> for Adc
323317
where
324318
WORD: From<u16>,

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