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Merge pull request #74 from stm32-rs/feature/rcc-refactoring
RCC refactoring
2 parents 2daf31b + 946d036 commit 50b3ab4

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16 files changed

+177
-94
lines changed

16 files changed

+177
-94
lines changed

‎src/analog/adc.rs‎

Lines changed: 0 additions & 4 deletions
Original file line numberDiff line numberDiff line change
@@ -304,10 +304,6 @@ where
304304
type Error = ();
305305

306306
fn prepare_injected(&mut self, _pin: &mut PIN, triger_source: InjTrigSource) {
307-
// set the clock mode to synchronous one
308-
// self.rb.cfgr2.ckmode().bits(CLCOKMODE) // CLOCKMODE = 01 or 10 for PCLK/2 or PCLK/4
309-
310-
// self.set_injected_trigger_source(triger_source as InjTrigSource);
311307
self.rb
312308
.cfgr1
313309
.modify(|_, w| unsafe { w.exten().bits(1).extsel().bits(triger_source as u8) });

‎src/analog/dac.rs‎

Lines changed: 20 additions & 7 deletions
Original file line numberDiff line numberDiff line change
@@ -5,7 +5,7 @@ use core::mem::MaybeUninit;
55

66
use crate::gpio::gpioa::{PA4, PA5};
77
use crate::gpio::DefaultMode;
8-
use crate::rcc::Rcc;
8+
use crate::rcc::*;
99
use crate::stm32::DAC;
1010
use hal::blocking::delay::DelayUs;
1111

@@ -74,16 +74,29 @@ impl Pins<DAC> for (PA4<DefaultMode>, PA5<DefaultMode>) {
7474
type Output = (Channel1<Disabled>, Channel2<Disabled>);
7575
}
7676

77+
impl Enable for DAC {
78+
fn enable(rcc: &mut Rcc) {
79+
rcc.rb.apbenr1.modify(|_, w| w.dac1en().set_bit());
80+
}
81+
82+
fn disable(rcc: &mut Rcc) {
83+
rcc.rb.apbenr1.modify(|_, w| w.dac1en().clear_bit());
84+
}
85+
}
86+
87+
impl Reset for DAC {
88+
fn reset(rcc: &mut Rcc) {
89+
rcc.rb.apbrstr1.modify(|_, w| w.dac1rst().set_bit());
90+
rcc.rb.apbrstr1.modify(|_, w| w.dac1rst().clear_bit());
91+
}
92+
}
93+
7794
pub fn dac<PINS>(_dac: DAC, _pins: PINS, rcc: &mut Rcc) -> PINS::Output
7895
where
7996
PINS: Pins<DAC>,
8097
{
81-
// Enable DAC clocks
82-
rcc.rb.apbenr1.modify(|_, w| w.dac1en().set_bit());
83-
84-
// Reset DAC
85-
rcc.rb.apbrstr1.modify(|_, w| w.dac1rst().set_bit());
86-
rcc.rb.apbrstr1.modify(|_, w| w.dac1rst().clear_bit());
98+
DAC::enable(rcc);
99+
DAC::reset(rcc);
87100

88101
#[allow(clippy::uninit_assumed_init)]
89102
unsafe {

‎src/dma.rs‎

Lines changed: 1 addition & 1 deletion
Original file line numberDiff line numberDiff line change
@@ -308,7 +308,7 @@ macro_rules! dma {
308308

309309
// NOTE(unsafe) atomic write to a stateless register
310310
unsafe {
311-
&(*DMA::ptr()).ifcr.write(|w| match event {
311+
let _ = &(*DMA::ptr()).ifcr.write(|w| match event {
312312
HalfTransfer => w.$chtifi().set_bit(),
313313
TransferComplete => w.$ctcifi().set_bit(),
314314
TransferError => w.$cteifi().set_bit(),

‎src/gpio.rs‎

Lines changed: 1 addition & 1 deletion
Original file line numberDiff line numberDiff line change
@@ -313,7 +313,7 @@ macro_rules! gpio {
313313
pub fn listen(self, edge: SignalEdge, exti: &mut EXTI) -> $PXi<Input<Floating>> {
314314
let offset = 2 * $i;
315315
unsafe {
316-
&(*$GPIOX::ptr()).pupdr.modify(|r, w| {
316+
let _ = &(*$GPIOX::ptr()).pupdr.modify(|r, w| {
317317
w.bits(r.bits() & !(0b11 << offset))
318318
});
319319
&(*$GPIOX::ptr()).moder.modify(|r, w| {

‎src/i2c.rs‎

Lines changed: 20 additions & 7 deletions
Original file line numberDiff line numberDiff line change
@@ -3,7 +3,7 @@ use hal::blocking::i2c::{Read, Write, WriteRead};
33

44
use crate::gpio::{gpioa::*, gpiob::*};
55
use crate::gpio::{AltFunction, OpenDrain, Output};
6-
use crate::rcc::Rcc;
6+
use crate::rcc::*;
77
use crate::stm32::{I2C1, I2C2};
88
use crate::time::Hertz;
99
use core::cmp;
@@ -176,6 +176,23 @@ macro_rules! i2c {
176176
}
177177
)+
178178

179+
impl Enable for $I2CX {
180+
fn enable(rcc: &mut Rcc){
181+
rcc.rb.apbenr1.modify(|_, w| w.$i2cxen().set_bit());
182+
}
183+
184+
fn disable(rcc: &mut Rcc) {
185+
rcc.rb.apbenr1.modify(|_, w| w.$i2cxen().clear_bit());
186+
}
187+
}
188+
189+
impl Reset for $I2CX {
190+
fn reset(rcc: &mut Rcc){
191+
rcc.rb.apbrstr1.modify(|_, w| w.$i2crst().set_bit());
192+
rcc.rb.apbrstr1.modify(|_, w| w.$i2crst().clear_bit());
193+
}
194+
}
195+
179196
impl I2cExt<$I2CX> for $I2CX {
180197
fn i2c<SDA, SCL>(
181198
self,
@@ -201,12 +218,8 @@ macro_rules! i2c {
201218
SDA: SDAPin<$I2CX>,
202219
SCL: SCLPin<$I2CX>,
203220
{
204-
// Enable clock for I2C
205-
rcc.rb.apbenr1.modify(|_, w| w.$i2cxen().set_bit());
206-
207-
// Reset I2C
208-
rcc.rb.apbrstr1.modify(|_, w| w.$i2crst().set_bit());
209-
rcc.rb.apbrstr1.modify(|_, w| w.$i2crst().clear_bit());
221+
$I2CX::enable(rcc);
222+
$I2CX::reset(rcc);
210223

211224
// Make sure the I2C unit is disabled so we can configure it
212225
i2c.cr1.modify(|_, w| w.pe().clear_bit());

‎src/lib.rs‎

Lines changed: 0 additions & 1 deletion
Original file line numberDiff line numberDiff line change
@@ -46,7 +46,6 @@ pub use crate::stm32::interrupt;
4646

4747
pub mod analog;
4848
pub mod crc;
49-
pub mod delay;
5049
pub mod dma;
5150
pub mod dmamux;
5251
pub mod exti;

‎src/prelude.rs‎

Lines changed: 1 addition & 1 deletion
Original file line numberDiff line numberDiff line change
@@ -16,7 +16,7 @@ pub use crate::analog::dac::DacExt as _;
1616
#[cfg(any(feature = "stm32g071", feature = "stm32g081"))]
1717
pub use crate::analog::dac::DacOut as _;
1818
pub use crate::crc::CrcExt as _;
19-
pub use crate::delay::DelayExt as _;
19+
pub use crate::timer::delay::DelayExt as _;
2020
// pub use crate::dma::CopyDma as _;
2121
pub use crate::dma::DmaExt as _;
2222
// pub use crate::dma::ReadDma as _;

‎src/rcc/mod.rs‎

Lines changed: 11 additions & 0 deletions
Original file line numberDiff line numberDiff line change
@@ -347,3 +347,14 @@ impl RccExt for RCC {
347347
self.constrain().freeze(rcc_cfg)
348348
}
349349
}
350+
351+
/// Enable/disable peripheral
352+
pub trait Enable {
353+
fn enable(rcc: &mut Rcc);
354+
fn disable(rcc: &mut Rcc);
355+
}
356+
357+
/// Reset peripheral
358+
pub trait Reset {
359+
fn reset(rcc: &mut Rcc);
360+
}

‎src/serial/usart.rs‎

Lines changed: 24 additions & 3 deletions
Original file line numberDiff line numberDiff line change
@@ -6,7 +6,7 @@ use crate::dmamux::DmaMuxIndex;
66
use crate::gpio::AltFunction;
77
use crate::gpio::{gpioa::*, gpiob::*, gpioc::*, gpiod::*};
88
use crate::prelude::*;
9-
use crate::rcc::Rcc;
9+
use crate::rcc::*;
1010
use crate::stm32::*;
1111

1212
use cortex_m::interrupt;
@@ -332,6 +332,16 @@ macro_rules! uart_basic {
332332
($USARTX:ident,
333333
$usartX:ident, $apbXenr:ident, $usartXen:ident, $clk_mul:expr
334334
) => {
335+
impl Enable for $USARTX {
336+
fn enable(rcc: &mut Rcc) {
337+
rcc.rb.$apbXenr.modify(|_, w| w.$usartXen().set_bit());
338+
}
339+
340+
fn disable(rcc: &mut Rcc) {
341+
rcc.rb.$apbXenr.modify(|_, w| w.$usartXen().clear_bit());
342+
}
343+
}
344+
335345
impl SerialExt<$USARTX, BasicConfig> for $USARTX {
336346
fn usart<TX, RX>(
337347
self,
@@ -361,7 +371,8 @@ macro_rules! uart_basic {
361371
RX: RxPin<$USARTX>,
362372
{
363373
// Enable clock for USART
364-
rcc.rb.$apbXenr.modify(|_, w| w.$usartXen().set_bit());
374+
$USARTX::enable(rcc);
375+
365376
let clk = rcc.clocks.apb_clk.0 as u64;
366377
let bdr = config.baudrate.0 as u64;
367378
let div = ($clk_mul * clk) / bdr;
@@ -462,6 +473,16 @@ macro_rules! uart_full {
462473
($USARTX:ident,
463474
$usartX:ident, $apbXenr:ident, $usartXen:ident, $clk_mul:expr
464475
) => {
476+
impl Enable for $USARTX {
477+
fn enable(rcc: &mut Rcc) {
478+
rcc.rb.$apbXenr.modify(|_, w| w.$usartXen().set_bit());
479+
}
480+
481+
fn disable(rcc: &mut Rcc) {
482+
rcc.rb.$apbXenr.modify(|_, w| w.$usartXen().clear_bit());
483+
}
484+
}
485+
465486
impl SerialExt<$USARTX, FullConfig> for $USARTX {
466487
fn usart<TX, RX>(
467488
self,
@@ -491,7 +512,7 @@ macro_rules! uart_full {
491512
RX: RxPin<$USARTX>,
492513
{
493514
// Enable clock for USART
494-
rcc.rb.$apbXenr.modify(|_, w| w.$usartXen().set_bit());
515+
$USARTX::enable(rcc);
495516

496517
let clk = rcc.clocks.apb_clk.0 as u64;
497518
let bdr = config.baudrate.0 as u64;

‎src/spi.rs‎

Lines changed: 20 additions & 5 deletions
Original file line numberDiff line numberDiff line change
@@ -1,5 +1,5 @@
11
use crate::gpio::{gpioa::*, gpiob::*, gpioc::*, gpiod::*, AltFunction, DefaultMode};
2-
use crate::rcc::Rcc;
2+
use crate::rcc::*;
33
use crate::stm32::{SPI1, SPI2};
44
use crate::time::Hertz;
55
use core::ptr;
@@ -137,6 +137,23 @@ macro_rules! spi {
137137
}
138138
)*
139139

140+
impl Enable for $SPIX {
141+
fn enable(rcc: &mut Rcc){
142+
rcc.rb.$apbXenr.modify(|_, w| w.$spiXen().set_bit());
143+
}
144+
145+
fn disable(rcc: &mut Rcc) {
146+
rcc.rb.$apbXenr.modify(|_, w| w.$spiXen().clear_bit());
147+
}
148+
}
149+
150+
impl Reset for $SPIX {
151+
fn reset(rcc: &mut Rcc){
152+
rcc.rb.$apbXrst.modify(|_, w| w.$spiXrst().set_bit());
153+
rcc.rb.$apbXrst.modify(|_, w| w.$spiXrst().clear_bit());
154+
}
155+
}
156+
140157
impl<PINS: Pins<$SPIX>> Spi<$SPIX, PINS> {
141158
pub fn $spiX<T>(
142159
spi: $SPIX,
@@ -148,10 +165,8 @@ macro_rules! spi {
148165
where
149166
T: Into<Hertz>
150167
{
151-
// Enable clock for SPI
152-
rcc.rb.$apbXenr.modify(|_, w| w.$spiXen().set_bit());
153-
rcc.rb.$apbXrst.modify(|_, w| w.$spiXrst().set_bit());
154-
rcc.rb.$apbXrst.modify(|_, w| w.$spiXrst().clear_bit());
168+
$SPIX::enable(rcc);
169+
$SPIX::reset(rcc);
155170

156171
// disable SS output
157172
spi.cr2.write(|w| w.ssoe().clear_bit());

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