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andresvandresv
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Merge pull request #149 from rblaze/stm32g0-15
Update stm32g0 to 0.15.1
2 parents 8f6e6bb + e4c88d2 commit 7b45680

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11 files changed

+73
-89
lines changed

11 files changed

+73
-89
lines changed

‎Cargo.toml

Lines changed: 1 addition & 1 deletion
Original file line numberDiff line numberDiff line change
@@ -21,7 +21,7 @@ nb = "1.0.0"
2121
fugit = "0.3.5"
2222

2323
[dependencies.stm32g0]
24-
version = "0.14.0"
24+
version = "0.15.1"
2525
features = ["rt"]
2626

2727
[dependencies.bare-metal]

‎src/analog/adc.rs

Lines changed: 10 additions & 17 deletions
Original file line numberDiff line numberDiff line change
@@ -132,12 +132,9 @@ impl Adc {
132132
/// Sets ADC source
133133
pub fn set_clock_source(&mut self, clock_source: ClockSource) {
134134
match clock_source {
135-
ClockSource::Pclk(div) => self
136-
.rb
137-
.cfgr2
138-
.modify(|_, w| unsafe { w.ckmode().bits(div as u8) }),
135+
ClockSource::Pclk(div) => self.rb.cfgr2.modify(|_, w| w.ckmode().bits(div as u8)),
139136
ClockSource::Async(div) => {
140-
self.rb.cfgr2.modify(|_, w| unsafe { w.ckmode().bits(0) });
137+
self.rb.cfgr2.modify(|_, w| w.ckmode().bits(0));
141138
self.rb
142139
.ccr
143140
.modify(|_, w| unsafe { w.presc().bits(div as u8) });
@@ -175,9 +172,7 @@ impl Adc {
175172
///
176173
/// Do not call if an ADC reading is ongoing.
177174
pub fn set_calibration(&mut self, calfact: CalibrationFactor) {
178-
self.rb
179-
.calfact
180-
.write(|w| unsafe { w.calfact().bits(calfact.0) });
175+
self.rb.calfact.write(|w| w.calfact().bits(calfact.0));
181176
}
182177

183178
/// Set the Adc sampling time
@@ -204,9 +199,7 @@ impl Adc {
204199

205200
/// Oversampling of adc according to datasheet of stm32g0, when oversampling is enabled
206201
pub fn set_oversampling_ratio(&mut self, ratio: OversamplingRatio) {
207-
self.rb
208-
.cfgr2
209-
.modify(|_, w| unsafe { w.ovsr().bits(ratio as u8) });
202+
self.rb.cfgr2.modify(|_, w| w.ovsr().bits(ratio as u8));
210203
}
211204

212205
pub fn oversampling_enable(&mut self, enable: bool) {
@@ -348,7 +341,7 @@ where
348341
.cfgr1
349342
.modify(|_, w| unsafe { w.exten().bits(1).extsel().bits(triger_source as u8) });
350343

351-
self.rb.cfgr1.modify(|_, w| unsafe {
344+
self.rb.cfgr1.modify(|_, w| {
352345
w.res() // set ADC resolution bits (ADEN must be =0)
353346
.bits(self.precision as u8)
354347
.align() // set alignment bit is (ADSTART must be 0)
@@ -359,10 +352,10 @@ where
359352

360353
self.rb
361354
.smpr // set sampling time set 1 (ADSTART must be 0)
362-
.modify(|_, w| unsafe { w.smp1().bits(self.sample_time as u8) });
355+
.modify(|_, w| w.smp1().bits(self.sample_time as u8));
363356

364357
self.rb
365-
.chselr() // set activ channel acording chapter 15.12.9 (ADC_CFGR1; CHSELRMOD=0)
358+
.chselr0() // set active channel acording chapter 15.12.9 (ADC_CFGR1; CHSELRMOD=0)
366359
.modify(|_, w| unsafe { w.chsel().bits(1 << PIN::channel()) });
367360
}
368361
}
@@ -403,7 +396,7 @@ where
403396

404397
fn read(&mut self, _pin: &mut PIN) -> nb::Result<WORD, Self::Error> {
405398
self.power_up();
406-
self.rb.cfgr1.modify(|_, w| unsafe {
399+
self.rb.cfgr1.modify(|_, w| {
407400
w.res()
408401
.bits(self.precision as u8)
409402
.align()
@@ -412,10 +405,10 @@ where
412405

413406
self.rb
414407
.smpr
415-
.modify(|_, w| unsafe { w.smp1().bits(self.sample_time as u8) });
408+
.modify(|_, w| w.smp1().bits(self.sample_time as u8));
416409

417410
self.rb
418-
.chselr()
411+
.chselr0()
419412
.modify(|_, w| unsafe { w.chsel().bits(1 << PIN::channel()) });
420413

421414
self.rb.isr.modify(|_, w| w.eos().set_bit());

‎src/analog/dac.rs

Lines changed: 18 additions & 18 deletions
Original file line numberDiff line numberDiff line change
@@ -106,8 +106,8 @@ macro_rules! dac {
106106
pub fn enable(self) -> $CX<Enabled> {
107107
let dac = unsafe { &(*DAC::ptr()) };
108108

109-
dac.dac_mcr.modify(|_, w| unsafe { w.$mode().bits(1) });
110-
dac.dac_cr.modify(|_, w| w.$en().set_bit());
109+
dac.mcr.modify(|_, w| unsafe { w.$mode().bits(1) });
110+
dac.cr.modify(|_, w| w.$en().set_bit());
111111

112112
$CX {
113113
_enabled: PhantomData,
@@ -117,8 +117,8 @@ macro_rules! dac {
117117
pub fn enable_unbuffered(self) -> $CX<EnabledUnbuffered> {
118118
let dac = unsafe { &(*DAC::ptr()) };
119119

120-
dac.dac_mcr.modify(|_, w| unsafe { w.$mode().bits(2) });
121-
dac.dac_cr.modify(|_, w| w.$en().set_bit());
120+
dac.mcr.modify(|_, w| unsafe { w.$mode().bits(2) });
121+
dac.cr.modify(|_, w| w.$en().set_bit());
122122

123123
$CX {
124124
_enabled: PhantomData,
@@ -128,8 +128,8 @@ macro_rules! dac {
128128
pub fn enable_generator(self, config: GeneratorConfig) -> $CX<WaveGenerator> {
129129
let dac = unsafe { &(*DAC::ptr()) };
130130

131-
dac.dac_mcr.modify(|_, w| unsafe { w.$mode().bits(1) });
132-
dac.dac_cr.modify(|_, w| unsafe {
131+
dac.mcr.modify(|_, w| unsafe { w.$mode().bits(1) });
132+
dac.cr.modify(|_, w| unsafe {
133133
w.$wave().bits(config.mode);
134134
w.$ten().set_bit();
135135
w.$mamp().bits(config.amp);
@@ -159,19 +159,19 @@ macro_rules! dac {
159159
T: DelayUs<u32>,
160160
{
161161
let dac = unsafe { &(*DAC::ptr()) };
162-
dac.dac_cr.modify(|_, w| w.$en().clear_bit());
163-
dac.dac_mcr.modify(|_, w| unsafe { w.$mode().bits(0) });
164-
dac.dac_cr.modify(|_, w| w.$cen().set_bit());
162+
dac.cr.modify(|_, w| w.$en().clear_bit());
163+
dac.mcr.modify(|_, w| unsafe { w.$mode().bits(0) });
164+
dac.cr.modify(|_, w| w.$cen().set_bit());
165165
let mut trim = 0;
166166
while true {
167-
dac.dac_ccr.modify(|_, w| unsafe { w.$trim().bits(trim) });
167+
dac.ccr.modify(|_, w| unsafe { w.$trim().bits(trim) });
168168
delay.delay_us(64_u32);
169-
if dac.dac_sr.read().$cal_flag().bit() {
169+
if dac.sr.read().$cal_flag().bit() {
170170
break;
171171
}
172172
trim += 1;
173173
}
174-
dac.dac_cr.modify(|_, w| w.$cen().clear_bit());
174+
dac.cr.modify(|_, w| w.$cen().clear_bit());
175175

176176
$CX {
177177
_enabled: PhantomData,
@@ -181,7 +181,7 @@ macro_rules! dac {
181181
/// Disable the DAC channel
182182
pub fn disable(self) -> $CX<Disabled> {
183183
let dac = unsafe { &(*DAC::ptr()) };
184-
dac.dac_cr.modify(|_, w| unsafe {
184+
dac.cr.modify(|_, w| unsafe {
185185
w.$en().clear_bit().$wave().bits(0).$ten().clear_bit()
186186
});
187187

@@ -209,7 +209,7 @@ macro_rules! dac {
209209
impl $CX<WaveGenerator> {
210210
pub fn trigger(&mut self) {
211211
let dac = unsafe { &(*DAC::ptr()) };
212-
dac.dac_swtrgr.write(|w| { w.$swtrig().set_bit() });
212+
dac.swtrgr.write(|w| { w.$swtrig().set_bit() });
213213
}
214214
}
215215
)+
@@ -239,8 +239,8 @@ dac!(
239239
cal_flag1,
240240
otrim1,
241241
mode1,
242-
dac_dhr12r1,
243-
dac_dor1,
242+
dhr12r1,
243+
dor1,
244244
dacc1dhr,
245245
wave1,
246246
mamp1,
@@ -254,8 +254,8 @@ dac!(
254254
cal_flag2,
255255
otrim2,
256256
mode2,
257-
dac_dhr12r2,
258-
dac_dor2,
257+
dhr12r2,
258+
dor2,
259259
dacc2dhr,
260260
wave2,
261261
mamp2,

‎src/dmamux.rs

Lines changed: 7 additions & 7 deletions
Original file line numberDiff line numberDiff line change
@@ -185,13 +185,13 @@ macro_rules! dma_mux {
185185
#[cfg(any(feature = "stm32g070", feature = "stm32g071", feature = "stm32g081"))]
186186
dma_mux!(
187187
channels: {
188-
C0: (ch0, dmamux_c0cr),
189-
C1: (ch1, dmamux_c1cr),
190-
C2: (ch2, dmamux_c2cr),
191-
C3: (ch3, dmamux_c3cr),
192-
C4: (ch4, dmamux_c4cr),
193-
C5: (ch5, dmamux_c5cr),
194-
C6: (ch6, dmamux_c6cr),
188+
C0: (ch0, c0cr),
189+
C1: (ch1, c1cr),
190+
C2: (ch2, c2cr),
191+
C3: (ch3, c3cr),
192+
C4: (ch4, c4cr),
193+
C5: (ch5, c5cr),
194+
C6: (ch6, c6cr),
195195
},
196196
);
197197

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