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rblazerblaze
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Cleanup unnecessary unsafe blocks
Some unsafe blocks still give warnings but can't be removed because of the non-matching register definitions.
1 parent 249fbba commit e4c88d2

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6 files changed

+39
-48
lines changed

6 files changed

+39
-48
lines changed

‎src/analog/adc.rs

Lines changed: 8 additions & 15 deletions
Original file line numberDiff line numberDiff line change
@@ -132,12 +132,9 @@ impl Adc {
132132
/// Sets ADC source
133133
pub fn set_clock_source(&mut self, clock_source: ClockSource) {
134134
match clock_source {
135-
ClockSource::Pclk(div) => self
136-
.rb
137-
.cfgr2
138-
.modify(|_, w| unsafe { w.ckmode().bits(div as u8) }),
135+
ClockSource::Pclk(div) => self.rb.cfgr2.modify(|_, w| w.ckmode().bits(div as u8)),
139136
ClockSource::Async(div) => {
140-
self.rb.cfgr2.modify(|_, w| unsafe { w.ckmode().bits(0) });
137+
self.rb.cfgr2.modify(|_, w| w.ckmode().bits(0));
141138
self.rb
142139
.ccr
143140
.modify(|_, w| unsafe { w.presc().bits(div as u8) });
@@ -175,9 +172,7 @@ impl Adc {
175172
///
176173
/// Do not call if an ADC reading is ongoing.
177174
pub fn set_calibration(&mut self, calfact: CalibrationFactor) {
178-
self.rb
179-
.calfact
180-
.write(|w| unsafe { w.calfact().bits(calfact.0) });
175+
self.rb.calfact.write(|w| w.calfact().bits(calfact.0));
181176
}
182177

183178
/// Set the Adc sampling time
@@ -204,9 +199,7 @@ impl Adc {
204199

205200
/// Oversampling of adc according to datasheet of stm32g0, when oversampling is enabled
206201
pub fn set_oversampling_ratio(&mut self, ratio: OversamplingRatio) {
207-
self.rb
208-
.cfgr2
209-
.modify(|_, w| unsafe { w.ovsr().bits(ratio as u8) });
202+
self.rb.cfgr2.modify(|_, w| w.ovsr().bits(ratio as u8));
210203
}
211204

212205
pub fn oversampling_enable(&mut self, enable: bool) {
@@ -348,7 +341,7 @@ where
348341
.cfgr1
349342
.modify(|_, w| unsafe { w.exten().bits(1).extsel().bits(triger_source as u8) });
350343

351-
self.rb.cfgr1.modify(|_, w| unsafe {
344+
self.rb.cfgr1.modify(|_, w| {
352345
w.res() // set ADC resolution bits (ADEN must be =0)
353346
.bits(self.precision as u8)
354347
.align() // set alignment bit is (ADSTART must be 0)
@@ -359,7 +352,7 @@ where
359352

360353
self.rb
361354
.smpr // set sampling time set 1 (ADSTART must be 0)
362-
.modify(|_, w| unsafe { w.smp1().bits(self.sample_time as u8) });
355+
.modify(|_, w| w.smp1().bits(self.sample_time as u8));
363356

364357
self.rb
365358
.chselr0() // set active channel acording chapter 15.12.9 (ADC_CFGR1; CHSELRMOD=0)
@@ -403,7 +396,7 @@ where
403396

404397
fn read(&mut self, _pin: &mut PIN) -> nb::Result<WORD, Self::Error> {
405398
self.power_up();
406-
self.rb.cfgr1.modify(|_, w| unsafe {
399+
self.rb.cfgr1.modify(|_, w| {
407400
w.res()
408401
.bits(self.precision as u8)
409402
.align()
@@ -412,7 +405,7 @@ where
412405

413406
self.rb
414407
.smpr
415-
.modify(|_, w| unsafe { w.smp1().bits(self.sample_time as u8) });
408+
.modify(|_, w| w.smp1().bits(self.sample_time as u8));
416409

417410
self.rb
418411
.chselr0()

‎src/i2c/blocking.rs

Lines changed: 25 additions & 25 deletions
Original file line numberDiff line numberDiff line change
@@ -37,7 +37,7 @@ macro_rules! flush_txdr {
3737
($i2c:expr) => {
3838
// If a pending TXIS flag is set, write dummy data to TXDR
3939
if $i2c.isr.read().txis().bit_is_set() {
40-
$i2c.txdr.write(|w| unsafe { w.txdata().bits(0) });
40+
$i2c.txdr.write(|w| w.txdata().bits(0));
4141
}
4242

4343
// If TXDR is not flagged as empty, write 1 to flush it
@@ -78,9 +78,9 @@ macro_rules! busy_wait {
7878
} else if isr.tcr().bit_is_set() {
7979
// This condition Will only happen when reload == 1 and sbr == 1 (slave) and nbytes was written.
8080
// Send a NACK, set nbytes to clear tcr flag
81-
$i2c.cr2.modify(|_, w| unsafe {
81+
$i2c.cr2.modify(|_, w|
8282
w.nack().set_bit().nbytes().bits(1 as u8)
83-
});
83+
);
8484
// Make one extra loop here to wait on the stop condition
8585
} else if isr.addr().bit_is_set() {
8686
// in case of a master write_read operation, this flag is the only exit for the function.
@@ -176,31 +176,31 @@ macro_rules! i2c {
176176
i2c.timingr.write(|w| unsafe { w.bits(timing_bits) });
177177

178178
// Enable the I2C processing
179-
i2c.cr1.modify(|_, w| unsafe {
179+
i2c.cr1.modify(|_, w|
180180
w.pe()
181181
.set_bit()
182182
.dnf()
183183
.bits(config.digital_filter)
184184
.anfoff()
185185
.bit(!config.analog_filter)
186-
});
186+
);
187187

188188
if config.slave_address_1 > 0 {
189-
i2c.oar1.write(|w| unsafe {
189+
i2c.oar1.write(|w|
190190
w.oa1().bits(config.slave_address_1)
191191
.oa1mode().bit(config.address_11bits)
192192
.oa1en().set_bit()
193-
});
193+
);
194194
// Enable acknowlidge control
195195
i2c.cr1.modify(|_, w| w.sbc().set_bit() );
196196
}
197197

198198
if config.slave_address_2 > 0 {
199-
i2c.oar2.write( |w| unsafe {
199+
i2c.oar2.write( |w|
200200
w.oa2msk().bits( config.slave_address_mask as u8)
201201
.oa2().bits(config.slave_address_2)
202202
.oa2en().set_bit()
203-
});
203+
);
204204
// Enable acknowlidge control
205205
i2c.cr1.modify(|_, w| w.sbc().set_bit() );
206206
}
@@ -263,7 +263,7 @@ macro_rules! i2c {
263263
// Set START and prepare to send `bytes`.
264264
// The START bit can be set even if the bus is BUSY or
265265
// I2C is in slave mode.
266-
self.i2c.cr2.write(|w| unsafe {
266+
self.i2c.cr2.write(|w|
267267
w
268268
// Set number of bytes to transfer
269269
.nbytes().bits(sndlen as u8)
@@ -278,23 +278,23 @@ macro_rules! i2c {
278278
.reload().clear_bit()
279279
// Start transfer
280280
.start().set_bit()
281-
});
281+
);
282282
let mut idx = 0;
283283
// Wait until we are allowed to send data
284284
// (START has been ACKed or last byte went through)
285285
// macro will return false when the tc bit is set
286286
for byte in snd_buffer {
287287
busy_wait!(self.i2c, txis, bit_is_set, idx, sndlen);
288288
// Put byte on the wire
289-
self.i2c.txdr.write(|w| unsafe { w.txdata().bits(*byte) });
289+
self.i2c.txdr.write(|w| w.txdata().bits(*byte) );
290290
idx += 1;
291291
}
292292
// Wait until the write finishes before beginning to read.
293293
let dummy = 0xFE;
294294
busy_wait!(self.i2c, tc, bit_is_set, idx, dummy );
295295

296296
// reSTART and prepare to receive bytes into `rcv_buffer`
297-
self.i2c.cr2.write(|w| unsafe {
297+
self.i2c.cr2.write(|w|
298298
w
299299
// Set number of bytes to transfer
300300
.nbytes().bits(rcvlen as u8)
@@ -309,7 +309,7 @@ macro_rules! i2c {
309309
.reload().clear_bit()
310310
// Start transfer
311311
.start().set_bit()
312-
});
312+
);
313313

314314
idx = 0;
315315
loop {
@@ -334,7 +334,7 @@ macro_rules! i2c {
334334
// This could be up to 50% of a bus cycle (ie. up to 0.5/freq)
335335
while self.i2c.cr2.read().start().bit_is_set() {};
336336

337-
self.i2c.cr2.modify(|_, w| unsafe {
337+
self.i2c.cr2.modify(|_, w|
338338
w
339339
// Start transfer
340340
.start().set_bit()
@@ -347,7 +347,7 @@ macro_rules! i2c {
347347
// Automatic end mode
348348
.autoend().set_bit()
349349
.reload().clear_bit()
350-
});
350+
);
351351

352352
let mut idx = 0;
353353
loop {
@@ -356,7 +356,7 @@ macro_rules! i2c {
356356

357357
// Put byte on the wire
358358
if idx < buflen {
359-
self.i2c.txdr.write(|w| unsafe { w.txdata().bits(bytes[idx]) });
359+
self.i2c.txdr.write(|w| w.txdata().bits(bytes[idx]) );
360360
idx += 1;
361361
}
362362
}
@@ -380,7 +380,7 @@ macro_rules! i2c {
380380
// Set START and prepare to receive bytes into `buffer`.
381381
// The START bit can be set even if the bus
382382
// is BUSY or I2C is in slave mode.
383-
self.i2c.cr2.modify(|_, w| unsafe {
383+
self.i2c.cr2.modify(|_, w|
384384
w
385385
// Start transfer
386386
.start().set_bit()
@@ -393,7 +393,7 @@ macro_rules! i2c {
393393
// automatic end mode
394394
.autoend().set_bit()
395395
.reload().clear_bit()
396-
});
396+
);
397397
let mut idx = 0;
398398
loop {
399399
// Wait until we have received something
@@ -447,10 +447,10 @@ macro_rules! i2c {
447447
assert!(buflen < 256 && buflen > 0);
448448

449449
// Set the nbytes and prepare to send bytes into `buffer`.
450-
self.i2c.cr2.modify(|_, w| unsafe {
450+
self.i2c.cr2.modify(|_, w|
451451
w.nbytes().bits( buflen as u8)
452452
.reload().clear_bit()
453-
});
453+
);
454454
// flush i2c tx register
455455
self.i2c.isr.write(|w| w.txe().set_bit());
456456
// end address phase, release clock stretching
@@ -463,13 +463,13 @@ macro_rules! i2c {
463463

464464
// Put byte on the wire
465465
if idx < buflen {
466-
self.i2c.txdr.write(|w| unsafe { w.txdata().bits(bytes[idx]) });
466+
self.i2c.txdr.write(|w| w.txdata().bits(bytes[idx]) );
467467
idx += 1;
468468
} else {
469469
// we will never reach here. In case the master wants to read more than buflen
470470
// the hardware will send 0xFF
471471
// Also means that on slave side we cannot detect this error case
472-
self.i2c.txdr.write(|w| unsafe { w.txdata().bits(0x21) });
472+
self.i2c.txdr.write(|w| w.txdata().bits(0x21) );
473473
}
474474
}
475475
}
@@ -480,13 +480,13 @@ macro_rules! i2c {
480480
assert!(buflen < 256 && buflen > 0);
481481

482482
// Set the nbytes START and prepare to receive bytes into `buffer`.
483-
self.i2c.cr2.modify(|_, w| unsafe {
483+
self.i2c.cr2.modify(|_, w|
484484
w
485485
// Set number of bytes to transfer: maximum as all incoming bytes will be ACK'ed
486486
.nbytes().bits(buflen as u8)
487487
// during sending nbytes automatically send a ACK, stretch clock after last byte
488488
.reload().set_bit()
489-
});
489+
);
490490
// end address phase, release clock stretching
491491
self.i2c.icr.write(|w|
492492
w.addrcf().set_bit()

‎src/serial/usart.rs

Lines changed: 2 additions & 2 deletions
Original file line numberDiff line numberDiff line change
@@ -603,7 +603,7 @@ macro_rules! uart_full {
603603
usart.cr2.reset();
604604
usart.cr3.reset();
605605

606-
usart.cr2.write(|w| unsafe {
606+
usart.cr2.write(|w| {
607607
w.stop()
608608
.bits(config.stopbits.bits())
609609
.txinv()
@@ -617,7 +617,7 @@ macro_rules! uart_full {
617617
if let Some(timeout) = config.receiver_timeout {
618618
usart.cr1.write(|w| w.rtoie().set_bit());
619619
usart.cr2.modify(|_, w| w.rtoen().set_bit());
620-
usart.rtor.write(|w| unsafe { w.rto().bits(timeout) });
620+
usart.rtor.write(|w| w.rto().bits(timeout));
621621
}
622622

623623
usart.cr3.write(|w| unsafe {

‎src/timer/mod.rs

Lines changed: 1 addition & 1 deletion
Original file line numberDiff line numberDiff line change
@@ -166,7 +166,7 @@ macro_rules! timers {
166166
let psc = cycles / 0xffff;
167167
let arr = cycles / (psc + 1);
168168

169-
self.tim.psc.write(|w| unsafe { w.psc().bits(psc as u16) });
169+
self.tim.psc.write(|w| w.psc().bits(psc as u16) );
170170
self.tim.arr.write(|w| unsafe { w.bits(arr) });
171171

172172
// Generate an update event so that PSC and ARR values are copied into their

‎src/timer/stopwatch.rs

Lines changed: 1 addition & 1 deletion
Original file line numberDiff line numberDiff line change
@@ -40,7 +40,7 @@ macro_rules! stopwatches {
4040
///
4141
/// The counter frequency is equal to the input clock divided by the prescaler + 1.
4242
pub fn set_prescaler(&mut self, prescaler: u16) {
43-
self.tim.psc.write(|w| unsafe { w.psc().bits(prescaler) });
43+
self.tim.psc.write(|w| w.psc().bits(prescaler) );
4444
self.tim.egr.write(|w| w.ug().set_bit());
4545
}
4646

‎src/watchdog.rs

Lines changed: 2 additions & 4 deletions
Original file line numberDiff line numberDiff line change
@@ -32,10 +32,8 @@ impl IndependedWatchdog {
3232
// Enable access to RLR/PR
3333
self.iwdg.kr.write(|w| unsafe { w.key().bits(0x5555) });
3434

35-
self.iwdg.pr.write(|w| unsafe { w.pr().bits(psc) });
36-
self.iwdg
37-
.rlr
38-
.write(|w| unsafe { w.rl().bits(reload as u16) });
35+
self.iwdg.pr.write(|w| w.pr().bits(psc));
36+
self.iwdg.rlr.write(|w| w.rl().bits(reload as u16));
3937

4038
while self.iwdg.sr.read().bits() > 0 {}
4139

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