Merge pull request #24 from mgottschlag/serial

Support for USART/UART/LPUART

Author: luctius

examples/uart-dma.rs

@@ -0,0 +1,77 @@
+#![deny(warnings)]
+#![deny(unsafe_code)]
+#![no_main]
+#![no_std]
+
+extern crate cortex_m_rt as rt;
+
+use core::fmt::Write;
+
+use hal::dma::{config::DmaConfig, stream::DMAExt, TransferExt};
+use hal::prelude::*;
+use hal::serial::*;
+use hal::{rcc, stm32};
+use stm32g4xx_hal as hal;
+
+use cortex_m_rt::entry;
+use log::info;
+
+#[macro_use]
+mod utils;
+
+#[entry]
+fn main() -> ! {
+    utils::logger::init();
+
+    let dp = stm32::Peripherals::take().expect("cannot take peripherals");
+    let cp = cortex_m::Peripherals::take().expect("cannot take core peripherals");
+
+    let rcc = dp.RCC.constrain();
+    let mut rcc = rcc.freeze(rcc::Config::hsi());
+
+    let streams = dp.DMA1.split(&rcc);
+    let config = DmaConfig::default()
+        .transfer_complete_interrupt(false)
+        .circular_buffer(false)
+        .memory_increment(true);
+
+    info!("Init UART");
+    let gpioa = dp.GPIOA.split(&mut rcc);
+    let tx = gpioa.pa2.into_alternate();
+    let rx = gpioa.pa3.into_alternate();
+    let mut usart = dp
+        .USART2
+        .usart(
+            tx,
+            rx,
+            FullConfig::default().baudrate(115200.bps()),
+            &mut rcc,
+        )
+        .unwrap();
+
+    let mut delay_syst = cp.SYST.delay(&rcc.clocks);
+    let mut led = gpioa.pa5.into_push_pull_output();
+
+    info!("Start writing");
+
+    writeln!(usart, "Hello without DMA\r").unwrap();
+
+    let tx_buffer = cortex_m::singleton!(: [u8; 17] = *b"Hello with DMA!\r\n").unwrap();
+
+    let (tx, _rx) = usart.split();
+
+    // Setup DMA for USART2 TX with dma channel 1.
+    let mut transfer =
+        streams
+            .0
+            .into_memory_to_peripheral_transfer(tx.enable_dma(), &mut tx_buffer[..], config);
+
+    transfer.start(|_tx| {});
+    loop {
+        while !transfer.get_transfer_complete_flag() {}
+
+        delay_syst.delay(1000.ms());
+        led.toggle().unwrap();
+        transfer.restart(|_tx| {});
+    }
+}

examples/uart-fifo.rs

@@ -0,0 +1,71 @@
+#![deny(warnings)]
+#![deny(unsafe_code)]
+#![no_main]
+#![no_std]
+
+extern crate cortex_m_rt as rt;
+
+use core::fmt::Write;
+
+use hal::prelude::*;
+use hal::serial::*;
+use hal::{rcc, stm32};
+use stm32g4xx_hal as hal;
+
+use cortex_m_rt::entry;
+use log::info;
+
+#[macro_use]
+mod utils;
+
+#[entry]
+fn main() -> ! {
+    utils::logger::init();
+
+    info!("start");
+    let dp = stm32::Peripherals::take().expect("cannot take peripherals");
+    let mut rcc = dp.RCC.freeze(rcc::Config::hsi());
+
+    info!("Init UART");
+    let gpioa = dp.GPIOA.split(&mut rcc);
+    let tx = gpioa.pa2.into_alternate();
+    let rx = gpioa.pa3.into_alternate();
+    let mut usart = dp
+        .USART2
+        .usart(
+            tx,
+            rx,
+            FullConfig::default()
+                .baudrate(115200.bps())
+                .fifo_enable()
+                .rx_fifo_enable_interrupt()
+                .rx_fifo_threshold(FifoThreshold::FIFO_4_BYTES),
+            &mut rcc,
+        )
+        .unwrap();
+
+    writeln!(usart, "Hello USART2\r\n").unwrap();
+
+    let (mut tx1, mut rx1) = usart.split();
+
+    let mut cnt = 0;
+    loop {
+        if rx1.fifo_threshold_reached() {
+            loop {
+                match rx1.read() {
+                    Err(nb::Error::WouldBlock) => {
+                        // no more data available in fifo
+                        break;
+                    }
+                    Err(nb::Error::Other(_err)) => {
+                        // Handle other error Overrun, Framing, Noise or Parity
+                    }
+                    Ok(byte) => {
+                        writeln!(tx1, "{}: {}\r", cnt, byte).unwrap();
+                        cnt += 1;
+                    }
+                }
+            }
+        }
+    }
+}

examples/uart.rs

@@ -0,0 +1,56 @@
+#![deny(warnings)]
+#![deny(unsafe_code)]
+#![no_main]
+#![no_std]
+
+use core::fmt::Write;
+
+use hal::prelude::*;
+use hal::serial::FullConfig;
+use hal::{rcc, stm32};
+use stm32g4xx_hal as hal;
+
+use cortex_m_rt::entry;
+use log::info;
+use nb::block;
+
+#[macro_use]
+mod utils;
+
+#[entry]
+fn main() -> ! {
+    utils::logger::init();
+
+    info!("start");
+    let dp = stm32::Peripherals::take().expect("cannot take peripherals");
+    let mut rcc = dp.RCC.freeze(rcc::Config::hsi());
+
+    info!("Init UART");
+    // on Nucleo-G474, the pins marked TX/RX are connected to USART1 by default, whereas USART2 is
+    // connected to the ST-Link's UART.
+    let gpioa = dp.GPIOA.split(&mut rcc);
+    let tx = gpioa.pa2.into_alternate();
+    let rx = gpioa.pa3.into_alternate();
+    let mut usart = dp
+        .USART2
+        .usart(tx, rx, FullConfig::default(), &mut rcc)
+        .unwrap();
+    /*let gpioc = dp.GPIOC.split(&mut rcc);
+    let tx = gpioc.pc4.into_alternate();
+    let rx = gpioc.pc5.into_alternate();
+    let mut usart = dp
+        .USART1
+        .usart(tx, rx, FullConfig::default(), &mut rcc)
+        .unwrap();*/
+
+    writeln!(usart, "Hello USART1\r\n").unwrap();
+
+    let mut cnt = 0;
+    loop {
+        match block!(usart.read()) {
+            Ok(byte) => writeln!(usart, "{}: {}\r", cnt, byte).unwrap(),
+            Err(e) => writeln!(usart, "E: {:?}\r", e).unwrap(),
+        };
+        cnt += 1;
+    }
+}

src/gpio.rs

@@ -72,6 +72,14 @@ pub const AF4: u8 = 4;
 pub const AF5: u8 = 5;
 pub const AF6: u8 = 6;
 pub const AF7: u8 = 7;
+pub const AF8: u8 = 8;
+pub const AF9: u8 = 9;
+pub const AF10: u8 = 10;
+pub const AF11: u8 = 11;
+pub const AF12: u8 = 12;
+pub const AF13: u8 = 13;
+pub const AF14: u8 = 14;
+pub const AF15: u8 = 15;
 
 /// External Interrupt Pin
 pub trait ExtiPin {

src/lib.rs

@@ -75,7 +75,7 @@ pub mod prelude;
 // pub mod qei;
 pub mod rcc;
 // pub mod rng;
-// pub mod serial;
+pub mod serial;
 pub mod signature;
 // pub mod spi;
 // pub mod stopwatch;

src/prelude.rs

@@ -31,7 +31,7 @@ pub use crate::rcc::MCOExt as _;
 pub use crate::rcc::RccExt as _;
 // pub use crate::rng::RngCore as _;
 // pub use crate::rng::RngExt as _;
-// pub use crate::serial::SerialExt as _;
+pub use crate::serial::SerialExt as _;
 // pub use crate::spi::SpiExt as _;
 pub use crate::time::U32Ext as _;
 // pub use crate::timer::opm::OpmExt as _;