Fix dma enable

Author: astapleton

src/spi.rs

@@ -503,7 +503,12 @@ impl<SPI: Instance, W: Word> Inner<SPI, W> {
         self.spi.cr1().modify(|_, w| w.spe().enabled());
     }
 
-    /// Enable SPI
+    #[inline]
+    pub fn start_transfer(&self) {
+        self.spi.cr1().modify(|_, w| w.cstart().started());
+    }
+
+    /// Disable SPI
     fn disable(&mut self) {
         self.spi.cr1().modify(|_, w| w.spe().disabled());
     }
@@ -583,13 +588,13 @@ impl<SPI: Instance, W: Word> Inner<SPI, W> {
     /// Disable DMA for both Rx and Tx
     #[inline]
     pub fn enable_tx_dma(&self) {
-        self.spi.cfg1().modify(|_, w| w.txdmaen().disabled());
+        self.spi.cfg1().modify(|_, w| w.txdmaen().enabled());
     }
 
     /// Disable DMA for both Rx and Tx
     #[inline]
     pub fn enable_rx_dma(&self) {
-        self.spi.cfg1().modify(|_, w| w.rxdmaen().disabled());
+        self.spi.cfg1().modify(|_, w| w.rxdmaen().enabled());
     }
 
     /// Disable DMA for both Rx and Tx
@@ -598,11 +603,6 @@ impl<SPI: Instance, W: Word> Inner<SPI, W> {
         self.spi.cfg1().modify(|_, w| w.rxdmaen().disabled().txdmaen().disabled());
     }
 
-    #[inline]
-    pub fn start_transfer(&self) {
-        self.spi.cr1().modify(|_, w| w.cstart().started());
-    }
-
     /// Read a single word from the receive data register
     #[inline(always)]
     fn read_data_reg(&mut self) -> W {

src/spi/dma.rs

@@ -182,7 +182,8 @@ where
     }
 
     pub fn wait_for_complete(&mut self) -> Result<(), Error> {
-        while !self.is_dma_complete()? {}
+        self.tx_transfer.wait_for_transfer_complete()?;
+        self.rx_transfer.wait_for_transfer_complete()?;
         self.spi.end_transaction();
         self.spi.disable_dma();
         Ok(())