fmt

Author: usbalbin

src/rcc.rs

@@ -617,19 +617,18 @@ impl Rcc {
         let rcc_hclk = self.config.rcc_hclk.unwrap_or(sys_ck.raw());
 
         // Estimate divisor
-        let (hpre_bits, hpre_div) =
-            match sys_ck.raw().div_ceil(rcc_hclk) {
-                0 => unreachable!(),
-                1 => (HPRE::Div1, 1),
-                2 => (HPRE::Div2, 2),
-                3..=5 => (HPRE::Div4, 4),
-                6..=11 => (HPRE::Div8, 8),
-                12..=39 => (HPRE::Div16, 16),
-                40..=95 => (HPRE::Div64, 64),
-                96..=191 => (HPRE::Div128, 128),
-                192..=383 => (HPRE::Div256, 256),
-                _ => (HPRE::Div512, 512),
-            };
+        let (hpre_bits, hpre_div) = match sys_ck.raw().div_ceil(rcc_hclk) {
+            0 => unreachable!(),
+            1 => (HPRE::Div1, 1),
+            2 => (HPRE::Div2, 2),
+            3..=5 => (HPRE::Div4, 4),
+            6..=11 => (HPRE::Div8, 8),
+            12..=39 => (HPRE::Div16, 16),
+            40..=95 => (HPRE::Div64, 64),
+            96..=191 => (HPRE::Div128, 128),
+            192..=383 => (HPRE::Div256, 256),
+            _ => (HPRE::Div512, 512),
+        };
 
         // Calculate real AHB clock
         let rcc_hclk = sys_ck.raw() / hpre_div;

src/rcc/pll.rs

@@ -151,8 +151,7 @@ fn vco_output_divider_setup(
 
     // Input divisor, resulting in a reference clock in the
     // range 2 to 16 MHz.
-    let pll_x_m_min =
-        pllsrc.div_ceil(*range.input_range.end());
+    let pll_x_m_min = pllsrc.div_ceil(*range.input_range.end());
     let pll_x_m_max = (pllsrc / range.input_range.start()).min(PLL_M_MAX);
 
     // Iterative search for the lowest m value that minimizes