Merge #278 #282

278: Add OCTOSPI Hyperbus support and an example for HyperRAM usage r=richardeoin a=richardeoin



282: improve spi traits r=richardeoin a=andrewgazelka

- rename to SPI traits to possibly better names
  -  `SpiAll` -> `HalSpi`
  - `SpiEnabled` -> `HalEnabledSpi`
  - `SpiDisabled` -> `HalDisabledSpi`
 
- `reset` no longer needs to take ownership of the given SPI peripheral 

Co-authored-by: Richard Meadows <[email protected]>
Co-authored-by: Andrew Gazelka <[email protected]>

Author: 3 people

Cargo.toml

@@ -165,6 +165,10 @@ required-features = ["xspi", "rm0433"]
 name = "octospi"
 required-features = ["xspi", "rm0468"]
 
+[[example]]
+name = "octospi_hyperram"
+required-features = ["xspi", "rm0468"]
+
 [[example]]
 name = "sdmmc"
 required-features = ["sdmmc", "rm0433"]

examples/octospi_hyperram.rs

@@ -0,0 +1,172 @@
+//! Example using a OCTOSPI HyperRAM in memory-mapped mode
+//!
+//! Tested on a STM32H735G-DK with a Cypress S70KL1281DABHI023
+
+#![deny(warnings)]
+#![no_main]
+#![no_std]
+
+use core::mem;
+use core::slice;
+
+#[macro_use]
+mod utilities;
+
+use cortex_m_rt::entry;
+use stm32h7xx_hal::rcc::rec::{OctospiClkSel, OctospiClkSelGetter};
+use stm32h7xx_hal::{gpio::Speed::High, pac, prelude::*, xspi::HyperbusConfig};
+
+use log::info;
+
+#[entry]
+fn main() -> ! {
+    utilities::logger::init();
+    let dp = pac::Peripherals::take().unwrap();
+
+    // Constrain and Freeze power
+    let pwr = dp.PWR.constrain();
+    let pwrcfg = example_power!(pwr).freeze();
+
+    // Constrain and Freeze clock
+    let rcc = dp.RCC.constrain();
+    let ccdr = rcc.sys_ck(320.mhz()).freeze(pwrcfg, &dp.SYSCFG);
+
+    // Octospi from HCLK at 160MHz
+    assert_eq!(ccdr.clocks.hclk().0, 160_000_000);
+    assert_eq!(
+        ccdr.peripheral.OCTOSPI1.get_kernel_clk_mux(),
+        OctospiClkSel::RCC_HCLK3
+    );
+
+    // Acquire the GPIO peripherals. This also enables the clock for
+    // the GPIOs in the RCC register.
+    let gpiog = dp.GPIOG.split(ccdr.peripheral.GPIOG);
+    let gpiob = dp.GPIOB.split(ccdr.peripheral.GPIOB);
+    let gpiof = dp.GPIOF.split(ccdr.peripheral.GPIOF);
+
+    let _tracweswo = gpiob.pb3.into_alternate_af0();
+
+    let _ncs = gpiog
+        .pg12
+        .into_alternate_af3()
+        .set_speed(High)
+        .internal_pull_up(true);
+    let _dqs = gpiof
+        .pf12
+        .into_alternate_af9()
+        .set_speed(High)
+        .internal_pull_up(true);
+    let _clk = gpiof
+        .pf4
+        .into_alternate_af9()
+        .set_speed(High)
+        .internal_pull_up(true);
+    let _io0 = gpiof
+        .pf0
+        .into_alternate_af9()
+        .set_speed(High)
+        .internal_pull_up(true);
+    let _io1 = gpiof
+        .pf1
+        .into_alternate_af9()
+        .set_speed(High)
+        .internal_pull_up(true);
+    let _io2 = gpiof
+        .pf2
+        .into_alternate_af9()
+        .set_speed(High)
+        .internal_pull_up(true);
+    let _io3 = gpiof
+        .pf3
+        .into_alternate_af9()
+        .set_speed(High)
+        .internal_pull_up(true);
+    let _io4 = gpiog
+        .pg0
+        .into_alternate_af9()
+        .set_speed(High)
+        .internal_pull_up(true);
+    let _io5 = gpiog
+        .pg1
+        .into_alternate_af9()
+        .set_speed(High)
+        .internal_pull_up(true);
+    let _io6 = gpiog
+        .pg10
+        .into_alternate_af3()
+        .set_speed(High)
+        .internal_pull_up(true);
+    let _io7 = gpiog
+        .pg11
+        .into_alternate_af9()
+        .set_speed(High)
+        .internal_pull_up(true);
+
+    info!("");
+    info!("stm32h7xx-hal example - OCTOSPI HyperRAM");
+    info!("");
+
+    // Initialise a HyperRAM on the OCTOSPI2 peripheral
+    let ram_slice = unsafe {
+        let hyperram_size = 16 * 1024 * 1024; // 16 MByte
+        let config = HyperbusConfig::new(80.mhz())
+            .device_size_bytes(24) // 16 Mbyte
+            .refresh_interval(4.us())
+            .read_write_recovery(4) // 50ns
+            .access_initial_latency(6);
+
+        let hyperram = dp.OCTOSPI2.octospi_hyperbus_unchecked(
+            config,
+            &ccdr.clocks,
+            ccdr.peripheral.OCTOSPI2,
+        );
+
+        info!("Created HyperRAM..");
+        info!("{}", hyperram);
+        info!("");
+
+        // Initialise and convert raw pointer to slice
+        let ram_ptr: *mut u32 = hyperram.init();
+        slice::from_raw_parts_mut(
+            ram_ptr,
+            hyperram_size / mem::size_of::<u32>(),
+        )
+    };
+
+    info!("Writing checkerboard pattern...");
+    for x in ram_slice.iter_mut() {
+        *x = 0xAA55AA55;
+    }
+    info!("Reading checkerboard pattern...");
+    for (i, x) in ram_slice.iter().enumerate() {
+        assert_eq!(
+            *x,
+            0xAA55AA55,
+            "Mismatch at address 0x{:x} (0x{:x} != 0xaa55aa55)",
+            i * 4,
+            *x
+        );
+    }
+
+    info!("Writing reverse checkerboard pattern...");
+    for x in ram_slice.iter_mut() {
+        *x = 0x55AA55AA;
+    }
+    info!("Reading reverse checkerboard pattern...");
+    for (i, x) in ram_slice.iter().enumerate() {
+        assert_eq!(
+            *x,
+            0x55AA55AA,
+            "Mismatch at address 0x{:x} (0x{:x} != 0x55aa55aa)",
+            i * 4,
+            *x
+        );
+    }
+
+    info!("Success!");
+    info!("");
+
+    loop {
+        cortex_m::asm::nop();
+    }
+}

src/dma/macros.rs

@@ -125,7 +125,7 @@ macro_rules! peripheral_target_instance {
             unsafe impl TargetAddress<M2P> for spi::Spi<$peripheral, spi::Disabled, $size> {
                 #[inline(always)]
                 fn address(&self) -> usize {
-                    use spi::SpiAll;
+                    use spi::HalSpi;
                     &self.inner().$txreg as *const _ as usize
                 }
 
@@ -137,7 +137,7 @@ macro_rules! peripheral_target_instance {
             unsafe impl TargetAddress<P2M> for spi::Spi<$peripheral, spi::Disabled, $size> {
                 #[inline(always)]
                 fn address(&self) -> usize {
-                    use spi::SpiAll;
+                    use spi::HalSpi;
                     &self.inner().$rxreg as *const _ as usize
                 }
 

src/prelude.rs

@@ -23,9 +23,9 @@ pub use crate::sai::SaiPdmExt as _stm32h7xx_hal_spi_SaiPdmExt;
 #[cfg(feature = "sdmmc")]
 pub use crate::sdmmc::SdmmcExt as _stm32h7xx_hal_sdmmc_SdmmcExt;
 pub use crate::serial::SerialExt as _stm32h7xx_hal_serial_SerialExt;
-pub use crate::spi::SpiAll as _stm32h7xx_hal_spi_SpiAll;
-pub use crate::spi::SpiDisabled as _stm32h7xx_hal_spi_SpiDisabled;
-pub use crate::spi::SpiEnabled as _stm32h7xx_hal_spi_SpiEnabled;
+pub use crate::spi::HalDisabledSpi as _stm32h7xx_hal_spi_HalDisabledSpi;
+pub use crate::spi::HalEnabledSpi as _stm32h7xx_hal_spi_HalEnabledSpi;
+pub use crate::spi::HalSpi as _stm32h7xx_hal_spi_HalSpi;
 pub use crate::spi::SpiExt as _stm32h7xx_hal_spi_SpiExt;
 pub use crate::time::U32Ext as _stm32h7xx_hal_time_U32Ext;
 pub use crate::timer::TimerExt as _stm32h7xx_hal_timer_TimerExt;

src/spi.rs

@@ -541,8 +541,10 @@ pub trait SpiExt<SPI, WORD>: Sized {
         CONFIG: Into<Config>;
 }
 
-pub trait SpiEnabled: SpiAll + FullDuplex<Self::Word, Error = Error> {
-    type Disabled: SpiDisabled<
+pub trait HalEnabledSpi:
+    HalSpi + FullDuplex<Self::Word, Error = Error>
+{
+    type Disabled: HalDisabledSpi<
         Spi = Self::Spi,
         Word = Self::Word,
         Enabled = Self,
@@ -556,11 +558,8 @@ pub trait SpiEnabled: SpiAll + FullDuplex<Self::Word, Error = Error> {
     /// disabled.
     fn disable(self) -> Self::Disabled;
 
-    /// Resets the SPI peripheral. This is just a call to [SpiEnabled::disable]
-    /// and [SpiDisabled::enable]
-    fn reset(self) -> Self {
-        self.disable().enable()
-    }
+    /// Resets the SPI peripheral.
+    fn reset(&mut self);
 
     /// Sets up a frame transaction with the given amount of data words.
     ///
@@ -585,9 +584,9 @@ pub trait SpiEnabled: SpiAll + FullDuplex<Self::Word, Error = Error> {
     fn end_transaction(&mut self) -> Result<(), Error>;
 }
 
-pub trait SpiDisabled: SpiAll {
+pub trait HalDisabledSpi: HalSpi {
     type Rec;
-    type Enabled: SpiEnabled<Spi = Self::Spi, Word = Self::Word>;
+    type Enabled: HalEnabledSpi<Spi = Self::Spi, Word = Self::Word>;
 
     /// Enables the SPI peripheral.
     /// Clears the MODF flag, the SSI flag, and sets the SPE bit.
@@ -611,7 +610,7 @@ pub trait SpiDisabled: SpiAll {
     fn free(self) -> (Self::Spi, Self::Rec);
 }
 
-pub trait SpiAll: Sized {
+pub trait HalSpi: Sized {
     type Spi;
     type Word;
 
@@ -681,7 +680,7 @@ macro_rules! spi {
             // For each $TY
             $(
 
-            impl Spi<$SPIX, Enabled, $TY> {
+                impl Spi<$SPIX, Enabled, $TY> {
                     fn $spiX<T, CONFIG>(
                         spi: $SPIX,
                         config: CONFIG,
@@ -805,14 +804,33 @@ macro_rules! spi {
                     }
                 }
 
-                impl SpiEnabled for Spi<$SPIX, Enabled, $TY> {
-                    type Disabled = Spi<Self::Spi, Disabled, Self::Word>;
-
-                    fn disable(self) -> Spi<$SPIX, Disabled, $TY> {
-                        // Master communication must be suspended before the peripheral is disabled
+                impl <Ed> Spi<$SPIX, Ed, $TY> {
+                    /// internally disable the SPI without changing its type-state
+                    fn internal_disable(&mut self) {
                         self.spi.cr1.modify(|_, w| w.csusp().requested());
                         while self.spi.sr.read().eot().is_completed() {}
                         self.spi.cr1.write(|w| w.ssi().slave_not_selected().spe().disabled());
+                    }
+
+                    /// internally enable the SPI without changing its type-state
+                    fn internal_enable(&mut self) {
+                        self.clear_modf(); // SPE cannot be set when MODF is set
+                        self.spi.cr1.write(|w| w.ssi().slave_not_selected().spe().enabled());
+                    }
+                }
+
+                impl HalEnabledSpi for Spi<$SPIX, Enabled, $TY> {
+                    type Disabled = Spi<Self::Spi, Disabled, Self::Word>;
+
+                    fn reset(&mut self) {
+                        self.internal_disable();
+                        self.internal_enable();
+                    }
+
+                    fn disable(mut self) -> Spi<$SPIX, Disabled, $TY> {
+                        // Master communication must be suspended before the peripheral is disabled
+                        self.internal_disable();
+
                         Spi {
                             spi: self.spi,
                             hardware_cs_mode: self.hardware_cs_mode,
@@ -859,13 +877,12 @@ macro_rules! spi {
                     }
                 }
 
-                impl SpiDisabled for Spi<$SPIX, Disabled, $TY> {
+                impl HalDisabledSpi for Spi<$SPIX, Disabled, $TY> {
                     type Rec = rec::$Rec;
                     type Enabled = Spi<Self::Spi, Enabled, Self::Word>;
 
                     fn enable(mut self) -> Self::Enabled {
-                        self.clear_modf(); // SPE cannot be set when MODF is set
-                        self.spi.cr1.write(|w| w.ssi().slave_not_selected().spe().enabled());
+                        self.internal_enable();
                         Spi {
                             spi: self.spi,
                             hardware_cs_mode: self.hardware_cs_mode,
@@ -895,7 +912,7 @@ macro_rules! spi {
                     }
                 }
 
-                impl<EN> SpiAll for Spi<$SPIX, EN, $TY>
+                impl<EN> HalSpi for Spi<$SPIX, EN, $TY>
                 {
                     type Word = $TY;
                     type Spi = $SPIX;