spi: fix clippy lint

.github/workflows/ci.yml

@@ -24,7 +24,7 @@ jobs:
           - "stm32wl5x_cm4"
           - "stm32wle5"
         toolchain:
-          - "1.62" # MSRV
+          - "1.85" # MSRV
           - "beta"
         exclude:
           - mcu: "stm32wl5x_cm0p"

CHANGELOG.md

@@ -9,7 +9,8 @@ and this project adheres to [Semantic Versioning](https://semver.org/spec/v2.0.0
 - Renamed function TcxoMode::set_txco_trim() to TcxoMode::set_tcxo_trim() to correct spelling.
 - Renamed enum CmdStatus::Avaliable to CmdStatus::Available to correct spelling.
 - Updated minimum `chrono` version to `0.4.23` to satisfy `cargo-audit`.
-- Changed minimum supported rust version from 1.60 to 1.62.
+- Changed the edition from 2021 to 2024.
+- Changed minimum supported rust version from 1.60 to 1.85.
 
 ### Fixed
 - Added a missing `must_use` in `SleepCfg::set_startup`.

Cargo.toml

@@ -43,3 +43,18 @@ incremental = false
 lto = false
 opt-level = 3 
 overflow-checks = false
+
+[workspace.package]
+edition = "2024"
+authors = ["Alex Martens <[email protected]>"]
+repository = "https://github.com/stm32-rs/stm32wlxx-hal"
+license = "MIT OR Apache-2.0"
+# To update version change:
+# * BSP versions
+# * BSP HAL dependency versions
+# * README
+# * BSP READMES
+# * lock file
+# * CHANGELOG Unreleased (URL and header)
+version = "0.6.1"
+rust-version = "1.85"  # update MSRV in CI, and shield in README

README.md

@@ -4,7 +4,7 @@
 [![stable-docs](https://img.shields.io/badge/docs-stable-blue)](https://docs.rs/stm32wlxx-hal/)
 [![nightly-docs](https://img.shields.io/badge/docs-nightly-black)](https://stm32-rs.github.io/stm32wlxx-hal/stm32wlxx_hal/index.html)
 [![crates.io](https://img.shields.io/crates/v/stm32wlxx-hal.svg)](https://crates.io/crates/stm32wlxx-hal)
-[![rustc](https://img.shields.io/badge/rustc-1.62+-blue.svg)](https://doc.rust-lang.org/cargo/reference/manifest.html#the-rust-version-field)
+[![rustc](https://img.shields.io/badge/rustc-1.85+-blue.svg)](https://doc.rust-lang.org/cargo/reference/manifest.html#the-rust-version-field)
 
 Embedded rust HAL (hardware abstraction layer) for the STM32WL series.
 

examples/Cargo.toml

@@ -1,10 +1,13 @@
 [package]
 name = "examples"
-version = "0.1.0"
 publish = false
-authors = ["Alex Martens <[email protected]>"]
-edition = "2021"
-license = "MIT OR Apache-2.0"
+
+authors.workspace = true
+edition.workspace = true
+license.workspace = true
+repository.workspace = true
+rust-version.workspace = true
+version.workspace = true
 
 [dependencies]
 cortex-m = { version = "0.7", features = ["critical-section-single-core"] }

examples/examples/buzzer.rs

@@ -12,7 +12,7 @@ use panic_probe as _; // panic handler
 use stm32wlxx_hal::{
     self as hal,
     cortex_m::{self, delay::Delay},
-    gpio::{pins, Output, PinState, PortA},
+    gpio::{Output, PinState, PortA, pins},
     pac,
     util::new_delay,
 };

examples/examples/gpio-blink.rs

@@ -8,7 +8,7 @@ use panic_probe as _; // panic handler
 use stm32wlxx_hal::{
     self as hal,
     cortex_m::{self, delay::Delay},
-    gpio::{pins, Output, PinState, PortB},
+    gpio::{Output, PinState, PortB, pins},
     pac,
     util::new_delay,
 };

examples/examples/gpio-button-irq.rs

@@ -7,7 +7,7 @@ use defmt_rtt as _; // global logger
 use panic_probe as _; // panic handler
 use stm32wlxx_hal::{
     self as hal, cortex_m,
-    gpio::{pins, Exti, ExtiTrg, Input, PortC, Pull},
+    gpio::{Exti, ExtiTrg, Input, PortC, Pull, pins},
     pac::{self, interrupt},
 };
 

examples/examples/gpio-button.rs

@@ -7,7 +7,7 @@ use defmt_rtt as _; // global logger
 use panic_probe as _; // panic handler
 use stm32wlxx_hal::{
     self as hal, cortex_m,
-    gpio::{pins, Input, PinState, PortC, Pull},
+    gpio::{Input, PinState, PortC, Pull, pins},
     pac,
 };
 

hal/Cargo.toml

@@ -2,22 +2,15 @@
 name = "stm32wlxx-hal"
 description = "Hardware abstraction layer for the STM32WL series microcontrollers."
 readme = "../README.md"
-
-# To update version change:
-# * BSP versions
-# * BSP HAL dependency versions
-# * README
-# * BSP READMES
-# * lock file
-# * CHANGELOG Unreleased (URL and header)
-version = "0.6.1"
-authors = ["Alex Martens <[email protected]>"]
-edition = "2021"
-rust-version = "1.62"  # update MSRV in CI, BSPs, and shield in README
-license = "MIT OR Apache-2.0"
 keywords = ["arm", "cortex-m", "stm32", "hal"]
 categories = ["embedded", "hardware-support", "no-std"]
-repository = "https://github.com/stm32-rs/stm32wlxx-hal"
+
+authors.workspace = true
+edition.workspace = true
+license.workspace = true
+repository.workspace = true
+rust-version.workspace = true
+version.workspace = true
 
 [features]
 stm32wl5x_cm0p = ["stm32wl/stm32wl5x_cm0p"]

hal/src/adc.rs

@@ -12,8 +12,8 @@
 #[cfg(not(feature = "stm32wl5x_cm0p"))]
 pub use pac::adc::cfgr2::{OVSR_A as OversampleRatio, OVSS_A as OversampleShift};
 
-use crate::gpio;
 use crate::Ratio;
+use crate::gpio;
 
 use super::pac;
 use core::{ptr::read_volatile, time::Duration};
@@ -522,8 +522,10 @@ impl Adc {
     /// [`new`]: Adc::new
     #[inline]
     pub unsafe fn steal() -> Adc {
-        Adc {
-            adc: pac::Peripherals::steal().ADC,
+        unsafe {
+            Adc {
+                adc: pac::Peripherals::steal().ADC,
+            }
         }
     }
 
@@ -712,7 +714,7 @@ impl Adc {
     #[cfg(feature = "rt")]
     #[inline]
     pub unsafe fn unmask_irq() {
-        pac::NVIC::unmask(pac::Interrupt::ADC)
+        unsafe { pac::NVIC::unmask(pac::Interrupt::ADC) }
     }
 
     /// Mask the ADC IRQ in the NVIC.
@@ -1294,7 +1296,7 @@ impl Adc {
     /// ```no_run
     /// use stm32wlxx_hal::{
     ///     adc::{self, Adc},
-    ///     gpio::{pins::B4, Analog, PortB},
+    ///     gpio::{Analog, PortB, pins::B4},
     ///     pac, rcc,
     ///     util::new_delay,
     /// };

hal/src/aes.rs

@@ -312,10 +312,12 @@ impl Aes {
     /// [`new`]: Aes::new
     #[inline]
     pub unsafe fn steal() -> Aes {
-        let dp: pac::Peripherals = pac::Peripherals::steal();
-        Aes {
-            aes: dp.AES,
-            swap_mode: SwapMode::None,
+        unsafe {
+            let dp: pac::Peripherals = pac::Peripherals::steal();
+            Aes {
+                aes: dp.AES,
+                swap_mode: SwapMode::None,
+            }
         }
     }
 
@@ -334,7 +336,7 @@ impl Aes {
     #[cfg(all(not(feature = "stm32wl5x_cm0p"), feature = "rt"))]
     #[inline]
     pub unsafe fn unmask_irq() {
-        pac::NVIC::unmask(pac::Interrupt::AES)
+        unsafe { pac::NVIC::unmask(pac::Interrupt::AES) }
     }
 
     fn set_key(&mut self, key: &[u32]) -> KeySize {
@@ -417,7 +419,7 @@ impl Aes {
             self.aes.dinr.write(|w| w.din().bits(din));
         }
 
-        let remain_dw: usize = 4 - ((block.len() + 3) / 4);
+        let remain_dw: usize = 4 - block.len().div_ceil(4);
         for _ in 0..remain_dw {
             self.aes.dinr.write(|w| w.din().bits(0));
         }
@@ -441,7 +443,7 @@ impl Aes {
             }
         }
 
-        let remain_dw: usize = 4 - ((block.len() + 3) / 4);
+        let remain_dw: usize = 4 - block.len().div_ceil(4);
         for _ in 0..remain_dw {
             let _: u32 = self.aes.doutr.read().bits();
         }

hal/src/dac.rs

@@ -2,7 +2,7 @@
 
 use super::pac;
 
-use crate::gpio::{pins::A10, Analog};
+use crate::gpio::{Analog, pins::A10};
 use pac::dac::mcr::MODE1_A;
 
 /// ADC modes that use the A10 output pin
@@ -133,10 +133,12 @@ impl Dac {
     ///
     /// [`new`]: Dac::new
     pub unsafe fn steal() -> Dac {
-        let dp: pac::Peripherals = pac::Peripherals::steal();
-        Dac {
-            dac: dp.DAC,
-            out: None,
+        unsafe {
+            let dp: pac::Peripherals = pac::Peripherals::steal();
+            Dac {
+                dac: dp.DAC,
+                out: None,
+            }
         }
     }
 
@@ -171,7 +173,7 @@ impl Dac {
     /// ```
     #[cfg(all(not(feature = "stm32wl5x_cm0p"), feature = "rt"))]
     pub unsafe fn unmask_irq() {
-        pac::NVIC::unmask(pac::Interrupt::DAC)
+        unsafe { pac::NVIC::unmask(pac::Interrupt::DAC) }
     }
 
     /// Mask the DAC interrupt.
@@ -345,7 +347,7 @@ impl Dac {
     /// ```no_run
     /// use stm32wlxx_hal::{
     ///     dac::{Dac, ModeChip, ModePin},
-    ///     gpio::{pins, Analog, PortA},
+    ///     gpio::{Analog, PortA, pins},
     ///     pac,
     /// };
     ///

hal/src/dma/cr.rs

@@ -803,11 +803,7 @@ impl Cr {
     /// ```
     #[must_use = "set_enable returns a modified Cr"]
     pub const fn set_enable(self, en: bool) -> Cr {
-        if en {
-            self.enable()
-        } else {
-            self.disable()
-        }
+        if en { self.enable() } else { self.disable() }
     }
 
     /// Enable the DMA peripheral.

hal/src/dma/mod.rs

@@ -166,7 +166,7 @@ pub trait DmaCh: sealed::DmaOps {
     /// Check if the transfer is complete.
     ///
     /// ```no_run
-    /// use stm32wlxx_hal::dma::{flags, DmaCh};
+    /// use stm32wlxx_hal::dma::{DmaCh, flags};
     ///
     /// # let dma = unsafe { stm32wlxx_hal::dma::AllDma::steal().d1.c1 };
     /// let xfer_cpl: bool = dma.flags() & flags::XFER_CPL != 0;
@@ -182,7 +182,7 @@ pub trait DmaCh: sealed::DmaOps {
     /// Check and clear all set flags.
     ///
     /// ```no_run
-    /// use stm32wlxx_hal::dma::{flags, DmaCh};
+    /// use stm32wlxx_hal::dma::{DmaCh, flags};
     ///
     /// # let mut dma = unsafe { stm32wlxx_hal::dma::AllDma::steal().d1.c1 };
     /// let flags: u8 = dma.flags();
@@ -214,7 +214,7 @@ pub trait DmaCh: sealed::DmaOps {
     ///   DMAMUX1 overrun interrupt (C2IMR2\[15\])
     #[inline]
     unsafe fn unmask_irq(&self) {
-        pac::NVIC::unmask(Self::IRQ)
+        unsafe { pac::NVIC::unmask(Self::IRQ) }
     }
 
     /// Mask the DMA interrupt in the NVIC.