docs(D): add instruction descriptions for D extension (riscv-software-src#1079)

Added long names and descriptions for instructions under the D
extension. Operational fields will be added in a separate PR, unless
someone is already working on them.

Author: sudo-apt-abdullah

backends/instructions_appendix/all_instructions.golden.adoc

@@ -6,13 +6,13 @@
 $schema: inst_schema.json#
 kind: instruction
 name: fadd.d
-long_name: Floating-point Add Double-precision
+long_name: Floating-Point Add Double-Precision
 description:
   - id: inst-fadd.d-behaviour
     normative: false
     text: |
-      `fadd.d` is analogous to `fadd.s` and performs double-precision floating-point addition between
-      `xs1` and `xs2` and writes the final result to `xd`.
+      `FADD.D` is analogous to `FADD.S` and performs double-precision floating-point addition between
+      _fs1_ and _fs2_ and writes the final result to _fd_.
 definedBy: D
 assembly: fd, fs1, fs2, rm
 encoding:

spec/std/isa/inst/D/fadd.d.yaml

@@ -6,9 +6,33 @@
 $schema: inst_schema.json#
 kind: instruction
 name: fclass.d
-long_name: No synopsis available
-description: |
-  No description available.
+long_name: Floating-Point Classify Double-Precision
+description:
+  - id: inst-fclass.d-behaviour
+    normative: false
+    text: |
+      `FCLASS.D` is defined analogously to its single-precision counterpart, but operates on double-precision operands.
+      It examines the value in floating-point register _fs1_ and writes to integer register _xd_ a 10-bit mask that
+      indicates the class of the floating point number.
+
+      The format of the mask is described in the table below. The corresponding bit in _xd_ will be set if the property
+      is true and clear otherwise. All other bits in _xd_ are cleared. Note that exactly one bit in xd will be set.
+
+      .Format of result of `fclass` instruction.
+      [%autowidth,float="center",align="center",cols="^,<",options="header",]
+      |===
+      |_xd_ bit |Meaning
+      |0 |_fs1_ is latexmath:[$-\infty$].
+      |1 |_fs1_ is a negative normal number.
+      |2 |_fs1_ is a negative subnormal number.
+      |3 |_fs1_ is latexmath:[$-0$].
+      |4 |_fs1_ is latexmath:[$+0$].
+      |5 |_fs1_ is a positive subnormal number.
+      |6 |_fs1_ is a positive normal number.
+      |7 |_fs1_ is latexmath:[$+\infty$].
+      |8 |_fs1_ is a signaling NaN.
+      |9 |_fs1_ is a quiet NaN.
+      |===
 definedBy: D
 assembly: xd, fs1
 encoding:

spec/std/isa/inst/D/fclass.d.yaml

@@ -6,13 +6,13 @@
 $schema: inst_schema.json#
 kind: instruction
 name: fcvt.d.l
-long_name: Floating-point Convert Long to Double-precision
+long_name: Floating-Point Convert Long to Double-Precision
 description:
   - id: inst-fcvt.d.l-behaviour
     normative: false
     text: |
-      `fcvt.d.l` converts a 64-bit signed integer, in integer register `xs1` into a double-precision
-      floating-point number in floating-point register `fd`.
+      `FCVT.D.L` converts a 64-bit signed integer, in integer register _xs1_ into a double-precision
+      floating-point number in floating-point register _fd_.
 definedBy: D
 assembly: fd, xs1, rm
 encoding:

spec/std/isa/inst/D/fcvt.d.l.yaml

@@ -6,13 +6,13 @@
 $schema: inst_schema.json#
 kind: instruction
 name: fcvt.d.lu
-long_name: Floating-point Convert Unsigned Long to Double-precision
+long_name: Floating-Point Convert Unsigned Long to Double-Precision
 description:
   - id: inst-fcvt.d.lu-behaviour
     normative: false
     text: |
-      `fcvt.d.lu` converts to or from a 64-bit unsigned integer, `xs1` into a double-precision
-      floating-point number in floating-point register `fd`.
+      `FCVT.D.LU` converts to or from a 64-bit unsigned integer, _xs1_ into a double-precision
+      floating-point number in floating-point register _fd_.
 definedBy: D
 assembly: fd, xs1, rm
 encoding:

spec/std/isa/inst/D/fcvt.d.lu.yaml

@@ -6,15 +6,15 @@
 $schema: inst_schema.json#
 kind: instruction
 name: fcvt.d.s
-long_name: Floating-point Convert Single-precision to Double-precision
+long_name: Floating-Point Convert Single-Precision to Double-Precision
 description:
   - id: inst-fcvt.d.s-behaviour
     normative: false
     text: |
-      The single-precision to double-precision conversion instruction, `fcvt.d.s` is encoded in the OP-FP
+      The single-precision to double-precision conversion instruction, `FCVT.D.S` is encoded in the OP-FP
       major opcode space and both the source and destination are floating-point registers. The `xs2` field
       encodes the datatype of the source, and the `fmt` field encodes the datatype of the destination.
-      `fcvt.d.s` will never round.
+      `FCVT.D.S` will never round.
 definedBy: D
 assembly: fd, fs1, rm
 encoding:

spec/std/isa/inst/D/fcvt.d.s.yaml

@@ -6,14 +6,14 @@
 $schema: inst_schema.json#
 kind: instruction
 name: fcvt.d.w
-long_name: Floating-point Convert Word to Double-precision
+long_name: Floating-Point Convert Word to Double-Precision
 description:
   - id: inst-fcvt.d.w-behaviour
     normative: false
     text: |
-      `fcvt.d.w` converts a 32-bit signed integer, in integer register `xs1` into a double-precision
-      floating-point number in floating-point register `fd`.
-      Note `fcvt.d.w` always produces an exact result and is unaffected by rounding mode.
+      `FCVT.D.W` converts a 32-bit signed integer, in integer register _xs1_ into a double-precision
+      floating-point number in floating-point register _fd_. Note `FCVT.D.W` always produces an exact
+      result and is unaffected by rounding mode.
 definedBy: D
 assembly: fd, xs1, rm
 encoding:

spec/std/isa/inst/D/fcvt.d.w.yaml

@@ -6,14 +6,14 @@
 $schema: inst_schema.json#
 kind: instruction
 name: fcvt.d.wu
-long_name: Floating-point Convert Unsigned Word to Double-precision
+long_name: Floating-Point Convert Unsigned Word to Double-Precision
 description:
   - id: inst-fcvt.d.wu-behaviour
     normative: false
     text: |
-      `fcvt.d.wu` converts a 32-bit unsigned integer in integer register `fs1` into a double-precision
-      floating-point number in floating-point register `fd`.
-      Note `fcvt.d.wu` always produces an exact result and is unaffected by rounding mode.
+      `FCVT.D.WU` converts a 32-bit unsigned integer in integer register _xs1_ into a double-precision
+      floating-point number in floating-point register _fd_. Note `FCVT.D.WU` always produces an exact
+      result and is unaffected by rounding mode.
 definedBy: D
 assembly: fd, xs1, rm
 encoding:

spec/std/isa/inst/D/fcvt.d.wu.yaml

@@ -6,13 +6,13 @@
 $schema: inst_schema.json#
 kind: instruction
 name: fcvt.l.d
-long_name: Floating-point Convert Double-precision to Long
+long_name: Floating-Point Convert Double-Precision to Long
 description:
   - id: inst-fcvt.l.d-behaviour
     normative: false
     text: |
-      `fcvt.l.d` converts a double-precision floating-point number in floating-point register `fs1`
-      to a signed 64-bit integer, in integer register `xd`.
+      `FCVT.L.D` converts a double-precision floating-point number in floating-point register _fs1_
+      to a signed 64-bit integer, in integer register _xd_.
 definedBy: D
 assembly: xd, fs1, rm
 encoding:

spec/std/isa/inst/D/fcvt.l.d.yaml

@@ -6,13 +6,13 @@
 $schema: inst_schema.json#
 kind: instruction
 name: fcvt.lu.d
-long_name: Floating-point Convert Double-precision to Unsigned Long
+long_name: Floating-Point Convert Double-Precision to Unsigned Long
 description:
   - id: inst-fcvt.lu.d-behaviour
     normative: false
     text: |
-      `fcvt.lu.d` converts a double-precision floating-point number in floating-point register `xs1`
-      to an unsigned 64-bit integer, in integer register `xd`.
+      `FCVT.LU.D` converts a double-precision floating-point number in floating-point register _fs1_
+      to an unsigned 64-bit integer, in integer register _xd_.
 definedBy: D
 assembly: xd, fs1, rm
 encoding: