add: register that contains clk frq

register located at0xFF000000 + 0

Author: SurfaceYellowDuck

tang20k/scr1/ip/ahb_slave_mux/ahb_slave_mux.sv

@@ -7,6 +7,7 @@ module ahb_slave_mux
                 input        [1:0]                   htrans,
                 input        [31:0]                  rdata_0,
                 input        [31:0]                  rdata_1,
+                input        [31:0]                  rdata_2,
                 input        [SLAVE_DEVISES_CNT-1:0] resp,
                 input        [SLAVE_DEVISES_CNT-1:0] readyout,
                 output logic [31:0]                  hrdata,
@@ -34,6 +35,11 @@ module ahb_slave_mux
                     hrdata = rdata_1;
                     hresp  = resp[1];
                 end
+                else if (local_hsel[2] == 1) begin
+                    hready = readyout[2];
+                    hrdata = rdata_2;
+                    hresp  = resp[2];
+                end
                 else begin
                     hready = 1'b1;
                     hrdata = 32'b0;

tang20k/scr1/scr1_arch_custom.svh

@@ -9,7 +9,7 @@
 `define SCR1_PTFM_SOC_ID            32'h21042600
 `define SCR1_PTFM_BLD_ID            32'h22011202
 `define SCR1_PTFM_CORE_CLK_FREQ     32'd27000000
-`define SLAVE_DEVISES_CNT           2
+`define SLAVE_DEVISES_CNT           3
 `define ROM_SIZE                    16384
 
 //`define SCR1_TRGT_FPGA_XILINX        // Uncomment if target platform is Xilinx FPGAs

tang20k/scr1/tang20k_scr1.sv

@@ -63,9 +63,9 @@ module tang20k_scr1
     logic                               sys_rst_n;
 
 
-    logic                      dmem_ready;
-    logic                      dmem_resp;
-    logic                      dmem_hsel;
+    logic                               dmem_ready;
+    logic                               dmem_resp;
+    logic                               dmem_hsel;
     `endif // SCR1_DBG_EN
 
     // --- SCR1 ---------------------------------------------
@@ -124,6 +124,9 @@ module tang20k_scr1
     logic [31:0]                        rtc_counter;
     logic                               tick_2Hz;
     logic                               heartbeat;
+
+    logic [31:0]                        core_frq = FPGA_TANG20K_CORE_CLK_FREQ;
+    logic                               ahb_core_frq_sel;
 
     // ==  ==  ==  ==  ==  ==  ==  ==  ==  ==  ==  ==  ==  ==  ==  ==  ==  ==  ==  ==  ==  ==  ==  ==  ==  ==  ==  = 
     //  Resets
@@ -288,6 +291,7 @@ module tang20k_scr1
     assign jtag_tck = JTAG_TCK;
     assign jtag_tms = JTAG_TMS;
     assign jtag_tdi = JTAG_TDI;
+
     assign JTAG_TDO = (jtag_tdo_en == 1'b1) ? jtag_tdo : 1'bZ;;
 
     assign LED2 = jtag_tck;
@@ -302,13 +306,14 @@ module tang20k_scr1
     assign LED5          =  1'b1;
 
 
+    assign ahb_core_frq_sel = ahb_dmem_haddr[31:16] == 16'b1111_1111_0000_0000;
     assign uart_hsel = ahb_dmem_haddr[31:16] == 16'b1111_1111_0000_0001;  //uart
     assign dmem_hsel = ahb_dmem_haddr[31:16] == 16'b1111_1111_1111_1111;   //rom
     assign imem_hsel = ahb_imem_haddr[31:16] == 16'b1111_1111_1111_1111;
 
-    assign hsel_     = {dmem_hsel, uart_hsel};
-    assign hreadyout = {dmem_ready, uart_hready};
-    assign hresp     = {dmem_resp, uart_hresp};
+    assign hsel_     = {ahb_core_frq_sel, dmem_hsel, uart_hsel};
+    assign hreadyout = {1'b1, dmem_ready, uart_hready};
+    assign hresp     = {1'b0, dmem_resp, uart_hresp};
 
 
     ahb_lite_uart16550
@@ -373,6 +378,7 @@ module tang20k_scr1
     .hsel_s (hsel_),
     .rdata_0 (hrdata_0),
     .rdata_1 (hrdata_1),
+    .rdata_2 (core_frq),
     .resp (hresp),
     .readyout (hreadyout),