syntacore · SurfaceYellowDuck · Nov 6, 2024 · Jan 15, 2025 · Feb 20, 2025
diff --git a/Makefile b/Makefile
@@ -12,10 +12,13 @@ all: riscv hex
 PLATFORM ?= arty_scr1
 
 apps = scbl
-
+ifeq ($(PLATFORM), tang_primer_20_k)
+ld-script?=scbl_lite.ld
+else
 ld-script?=scbl.ld
+endif
 
-FLAGS_MARCH ?= rv32im
+FLAGS_MARCH ?= rv32ima_zicsr
 FLAGS_MABI ?= ilp32
 
 PLATFORM_HDR=plf_$(PLATFORM).h
@@ -30,7 +33,11 @@ LIBS = -lgcc -lc
 LD = $(CC)
 LDFLAGS = -march=$(FLAGS_MARCH) -mabi=${FLAGS_MABI} -static -T common/$(ld-script) -Xlinker -nostdlib -nostartfiles -ffast-math -Wl,--gc-sections -Wl,-Map=$(@:.elf=.map)
 OBJDUMP = $(CROSS_COMPILE)objdump -w -x -s -S
+ifeq ($(PLATFORM), tang_primer_20_k)
+OBJCOPY = $(CROSS_COMPILE)objcopy -j .startup -j .vectors -j .text -j .rodata -j .srodata
+else
 OBJCOPY = $(CROSS_COMPILE)objcopy
+endif
 
 ifdef PLATFORM
 CFLAGS += -DPLATFORM=$(PLATFORM) -DPLATFORM_HDR=\"$(PLATFORM_HDR)\"
@@ -90,9 +97,12 @@ $(build_dir)/%.o: %.S | $(build_dir)
 
 # make Xilinx *.mem and Altera *.hex files
 $(apps_hex): $(build_dir)/%.hex: $(build_dir)/%.elf
+ifeq ($(PLATFORM), tang_primer_20_k)
+	hexdump -v -e '"%08x" "\n"' $(@:.hex=.bin) >> $(@:.hex=.mem)
+else
 	echo "@00000000" > $(@:.hex=.mem) && hexdump -v -e '4/1 "%02x" "\n"' $(@:.hex=.bin) >> $(@:.hex=.mem)
 	./mk_altera_hex.sh $(@:.hex=.bin) $@
-
+endif
 riscv: $(apps_elf)
 
 hex: $(apps_hex)

diff --git a/common/scbl_lite.ld b/common/scbl_lite.ld
@@ -0,0 +1,111 @@
+/**
+*  Syntacore SCR* infra
+*
+*  @copyright (C) Syntacore 2015-2017. All rights reserved.
+*  @author mn-sc
+*
+*  @brief Bare metal linker script
+**/
+
+OUTPUT_ARCH( "riscv" )
+ENTRY(_start)
+
+MEMORY {
+  RAM (rwx) : ORIGIN = 0xF0000000, LENGTH = 4K
+  ROM (rx) : ORIGIN = 0xFFFF0000, LENGTH = 32K
+}
+
+SEC_ALIGN = 32;
+
+STACK_SIZE = 2K;
+
+SECTIONS {
+
+  __start_of_ram : {
+    _end = .;
+  } > RAM
+
+  .stack : {
+    __STACK_START__ = .;
+      LONG(0);
+    . += STACK_SIZE - 4;
+    __C_STACK_TOP__ = .;
+    __STACK_END__ = .;
+  } >RAM
+
+  .bss : {
+    . = ALIGN(SEC_ALIGN);
+    __BSS_START__ = .;
+    *(.dynbss) *(.bss .bss.* .gnu.linkonce.b.*) *(COMMON)
+  } >RAM
+
+  .sbss : {
+    . = ALIGN(SEC_ALIGN);
+    *(.sbss .sbss.* .gnu.linkonce.sb.*)
+    *(.scommon)
+    . = ALIGN(0x10);
+    __BSS_END__ = .;
+  } >RAM
+
+  .sdata : {
+    . = ALIGN(SEC_ALIGN);
+    *(.sdata .sdata.* .gnu.linkonce.s.*)
+   __global_pointer$ = . + 0x800;
+  } >RAM
+
+  .data : {
+    . = ALIGN(SEC_ALIGN);
+    *(.data .data.*)
+  } >RAM
+
+  /* thread-local data segments */
+  .tdata : {
+    . = ALIGN(SEC_ALIGN);
+    _tls_data = .;
+    _tdata_begin = .;
+    KEEP(*(.tdata .tdata.*));
+    _tdata_end = .;
+    . = ALIGN(0x10);
+  } >RAM
+
+  .tbss : {
+    . = ALIGN(SEC_ALIGN);
+    _tbss_begin = .;
+    KEEP(*(.tbss .tbss.*));
+    . = ALIGN(SEC_ALIGN);
+    _tbss_end = .;
+  } >RAM
+
+  __TLS_SIZE__ = _tbss_end - _tdata_begin;
+
+  __TLS0_BASE__ = __C_STACK_TOP__ - __TLS_SIZE__;
+
+  .startup ORIGIN(ROM) : {
+    KEEP(*(.startup));
+  } >ROM
+
+  .vectors ORIGIN(ROM) + 0x300 : {
+    KEEP(*(.vectors));
+    . = ALIGN(0x100);
+  } >ROM = 0
+
+  .text ORIGIN(ROM) + 0x400 : {
+    . = ALIGN(SEC_ALIGN);  
+    __TEXT_START__ = .;
+    *(.text .text*)
+    KEEP(*(.init.text));
+    __TEXT_END__ = .;
+  } >ROM
+
+  .rodata : ALIGN(SEC_ALIGN) {
+    *(.rodata) *(.rodata.*) *(.gnu.linkonce.r.*)
+  } >ROM
+
+    .srodata : ALIGN(SEC_ALIGN) {
+    *(.srodata.cst16) *(.srodata.cst8) *(.srodata.cst4) *(.srodata.cst2) *(.srodata.*)
+  } >ROM
+
+  /DISCARD/ : {
+    *(.eh_frame .eh_frame.*)
+  }
+}
diff --git a/src/plf_tang_primer_20_k.h b/src/plf_tang_primer_20_k.h
@@ -0,0 +1,49 @@
+/// Syntacore SCR* framework
+///
+/// @copyright (C) Syntacore 2015-2017. All rights reserved.
+/// @author mn-sc
+///
+/// @brief platform specific configurations
+#ifndef PLATFORM_TANG_PRIMER_20_K_SCR1_CONFIG_H
+#define PLATFORM_TANG_PRIMER_20_K_SCR1_CONFIG_H
+#define PLF_CPU_NAME "SCR1"
+#define PLF_IMPL_STR "Syntacore FPGA"
+// RTC timebase: 1 MHZ, internal
+#define PLF_RTC_TIMEBASE 1000000
+// sys clk freq, MHz
+#define PLF_SYS_FREQ     27000000
+// cpu clk freq
+#define PLF_CPU_FREQ     PLF_SYS_FREQ
+//----------------------
+// memory configuration
+//----------------------
+#define PLF_TCM_BASE     (0xF0000000)
+#define PLF_TCM_SIZE     (4*1024)
+#define PLF_TCM_ATTR     0
+#define PLF_TCM_NAME     "TCM"
+#define PLF_MTIMER_BASE  (0xF0040000)
+#define PLF_MTIMER_SIZE  (0x1000)
+#define PLF_MTIMER_ATTR  0
+#define PLF_MTIMER_NAME  "MTimer"
+#define PLF_MMIO_BASE    (0xFF000000)
+#define PLF_MMIO_SIZE    (0x100000)
+#define PLF_MMIO_ATTR    0
+#define PLF_MMIO_NAME    "MMIO"
+#define PLF_OCROM_BASE   (0xFFFF0000)
+#define PLF_OCROM_SIZE   (32*1024)
+#define PLF_OCROM_ATTR   0
+#define PLF_OCROM_NAME   "On-Chip ROM"
+#define PLF_MEM_MAP                                                     \
+    {PLF_TCM_BASE, PLF_TCM_SIZE, PLF_TCM_ATTR, PLF_TCM_NAME},           \
+    {PLF_MTIMER_BASE, PLF_MTIMER_SIZE, PLF_MTIMER_ATTR, PLF_MTIMER_NAME}, \
+    {PLF_MMIO_BASE, PLF_MMIO_SIZE, PLF_MMIO_ATTR, PLF_MMIO_NAME},       \
+    {PLF_OCROM_BASE, PLF_OCROM_SIZE, PLF_OCROM_ATTR, PLF_OCROM_NAME}
+// FPGA UART port
+#define PLF_UART0_BASE   (PLF_MMIO_BASE + 0x10000)
+#define PLF_UART0_16550
+#define PLF_UART0_IRQ 0
+
+#define PLF_IRQ_MAP                      \
+        [0 ... 31] = ~0,                 \
+        [12] = PLF_UART0_IRQ
+#endif // PLATFORM_DE10LITE_SCR1_CONFIG_H
diff --git a/src/scbl.c b/src/scbl.c
@@ -17,9 +17,11 @@
 #define FW_VER "1.2"
 #define FW_VER_CFG "scr1_RC"
 #define COPYRIGHT_STR "Copyright (C) 2015-2021 Syntacore. All rights reserved."
-
+#ifdef PLATFORM_TANG_PRIMER_20_K_SCR1_CONFIG_H
+#define MAX_XMODEM_RX_LEN PLF_TCM_SIZE
+#else 
 #define MAX_XMODEM_RX_LEN PLF_MEM_SIZE
-
+#endif
 #define LEDS_TASK_DELAY_MS  200
 #define MAX_HEX_LEDS        8
 
@@ -126,9 +128,11 @@ static void cmd_plf_info(void *arg)
     hwinfo();
     uart_puts("Platform configuration:\n");
     uart_print_info();
-    leds_print_info();
-    dips_print_info();
-    btn_print_info();
+    #ifndef PLATFORM_TANG_PRIMER_20_K_SCR1_CONFIG_H
+        leds_print_info();
+        dips_print_info();
+        btn_print_info();
+    #endif
 }
 
 static void cmd_xload(void *arg)
@@ -304,8 +308,9 @@ int main(void)
 {
     scr_rtc_init();
     sc1f_uart_init();
-    sc1f_leds_init();
-
+    #ifndef PLATFORM_TANG_PRIMER_20_K_SCR1_CONFIG_H
+        sc1f_leds_init();
+    #endif
     show_header();
     hwinfo();
     usage();
@@ -319,9 +324,13 @@ int main(void)
 
         int c;
         while ((c = sc1f_uart_getch_nowait()) == -1) {
+            #ifndef PLATFORM_TANG_PRIMER_20_K_SCR1_CONFIG_H
             indication_tasks();
+            #endif
         }
+        #ifndef PLATFORM_TANG_PRIMER_20_K_SCR1_CONFIG_H
         sc1f_leds_set(0);
+        #endif
 
         const struct scbl_cmd *cmd = 0;