Correct MSWI/MTIMER interrupt IDs in ACLINT

[Mes0903]

The DTS previously set the MSWI and MTIMER interrupt numbers incorrectly, which appears in the 'interrupts-extended' fields of the MSWI and MTIMER nodes in 'riscv-harts.dtsi'.

The Linux guests didn't break before because both the timer and IPIs are exercised via SBI calls, and the emulator services them through the SBI handlers rather than by relying on OS-visible IRQ wiring. That masked the DTS error.

Nevertheless, fixing the mapping prevents confusion during future bring-up and aligns with the RISC-V interrupt numbering.

Specifically, the 'riscv-harts.dtsi' before corrected:

mswi0: mswi@4400000 {
  #interrupt-cells = <0>;
  #address-cells = <0>;
  interrupt-controller;
  interrupts-extended = <&cpu0_intc 7>;
  reg = <0x4400000 0x4000>;
  compatible = "riscv,aclint-mswi";
};

mtimer0: mtimer@4300000 {
  interrupts-extended = <&cpu0_intc 3>;
  reg = <0x4300000 0x8000>;
  compatible = "riscv,aclint-mtimer";
};

After corrected:

mswi0: mswi@4400000 {
  #interrupt-cells = <0>;
  #address-cells = <0>;
  interrupt-controller;
  interrupts-extended = <&cpu0_intc 3>;
  reg = <0x4400000 0x4000>;
  compatible = "riscv,aclint-mswi";
};

mtimer0: mtimer@4300000 {
  interrupts-extended = <&cpu0_intc 7>;
  reg = <0x4300000 0x8000>;
  compatible = "riscv,aclint-mtimer";
};

---

Summary by cubic

Fixes ACLINT DTS generation by correcting MSWI and MTIMER interrupt IDs to match RISC-V (MSWI=3, MTIMER=7). This aligns interrupts-extended wiring and prevents confusion during bring-up.

• Bug Fixes
  • Swapped mswi_list and mtimer_list in dtsi_template so MSWI maps to IRQ 3 and MTIMER to IRQ 7.
  • Generated riscv-harts.dtsi now uses <&cpuX_intc 3> for MSWI and <&cpuX_intc 7> for MTIMER.

[cubic-dev-ai]

No issues found across 1 file

[chiangkd]

Bit[7] corresponds to the Machine Timer Interrupt (MTI), while Bit[3] corresponds to the Machine Software Interrupt (MSI). I agree with making this change.

[jserv]

Thank @Mes0903 for contributing!