Assembler and Simulator This project implements a custom assembler and simulator for a simplified RISC-style instruction set architecture (ISA). The assembler converts assembly language instructions into machine code, and the simulator executes the generated machine code by simulating registers, memory, and control flow. The project demonstrates a strong understanding of computer architecture, low-level programming, and system-level execution.
🧩 Assembler
Converts assembly instructions into machine code
Supports multiple instruction formats (R, I, S, B, J)
Handles labels and branching
Performs basic syntax validation
Generates binary / hexadecimal output
⚙️ Simulator
Simulates CPU registers
Simulates main memory
Executes instructions step-by-step
Supports arithmetic, logical, load/store, and control instructions
Displays final register and memory states
🛠 Tech Stack
Language: Python / C++ (edit if needed)
Concepts Used:
Computer Architecture
Instruction Encoding & Decoding
Registers & Memory Management
Tools: Git, GitHub