Feature: Complete RISC-V baremetal support with automated qemu emulation #3254
Conversation
…under qemu emulation. This update introduces a complete bare-metal support for TensorFlow Lite Micro on riscv32 baremetal toolchain using system mode qemu, including: - A minimal bootloader: start.s initializes stack and frame pointers for program entry. - Linker script: linker.ld defines memory layout and section mapping. - Stub handling: stubs.cc provides minimal syscall stubs for bare-metal builds. - UART driver: debug_log.cc implements UART-based logging for TFLM. - Lightweight printf: lightweight_snprintf supports %s, %d, and %p without libc. - Documentation: README.md describes build and run steps for the riscv32_baremetal target.
… to final baremetal executable.
…m emulation for any example.
| @@ -0,0 +1,38 @@ | |||
| ### **RISC-V 32-Bit Bare-Metal Support** | |||
There was a problem hiding this comment.
The current setup appears to be highly specific to QEMU. If this is the case, perhaps we should rename riscv32_baremetal to riscv32_qemu for better clarity.
| @@ -0,0 +1,72 @@ | |||
| /* Copyright 2023 The TensorFlow Authors. All Rights Reserved. | |||
| #include <stdio.h> | ||
| #include "tensorflow/lite/micro/riscv32_baremetal/lightweight_snprintf.cc" | ||
|
|
||
| // UART definitions- Datasheet: https://pdos.csail.mit.edu/6.S081/2024/lec/16550.pdf |
There was a problem hiding this comment.
How about using Semihosting instead of having UART support here?
| @@ -0,0 +1,40 @@ | |||
| extern "C" { | |||
There was a problem hiding this comment.
This might not be necessary if Semihosting is used?
| -o $@ $< \ | ||
| $(MICROLITE_LIB_PATH) $(LDFLAGS) $(MICROLITE_LIBS) | ||
|
|
||
| # Build rules and object setup for the RISC-V 32-bit bare-metal target, |
There was a problem hiding this comment.
The primary Makefile should only contain common definitions. All platform-specific configurations must be moved into their respective target makefiles.
| # List of available examples | ||
| EXAMPLES := person_detection hello_world micro_speech person_detection_test hello_world_test micro_speech_test dtln_test | ||
|
|
||
| # Run a given example in QEMU using test_with_qemu.sh | ||
| $(EXAMPLES): | ||
| @$(TEST_SCRIPT) system-riscv32 - gen/riscv32_baremetal_x86_64_default_gcc/bin/$@ non_test_binary riscv32_baremetal |
There was a problem hiding this comment.
This doesn't seem like the best place for the examples instructions. Why do we need this?
| TARGET_TOOLCHAIN_PREFIX := riscv32-unknown-elf- | ||
|
|
||
| # Toolchain Path | ||
| TARGET_TOOLCHAIN_ROOT := /home/mips/riscv32/bin/ |
There was a problem hiding this comment.
I think this is the test code?
2 participants
Solves issue #3253
Adds full bare-metal RISC-V 32-bit support for TensorFlow Lite Micro, including a minimal bootloader, linker script, UART driver logging, stubs (all under tensorflow/lite/micro/riscv32_baremetal/), and a new target (riscv32_baremetal_makefile.inc) with QEMU full-system emulation. This enables running TFLM examples without any OS dependencies and improves embedded portability and testability.