test

7.33.0-stochrnd-40342

#40342: Correct sfpstochrnd encoding

test

7.33.0-checking-36930

#36930: Extend checking

Compiler update

• Check builtin argument values
• Remove erroneous sfpi getter function
• Rename internal sfpu vector type. This is not part of the user API
• Add copyexp function to copy the exponent from one vector to another.

7.33.0-vec_t-40182

#40182: Move raw sfpu vector type into implementation namespace

test

Remove vConstFloat

detail

detail

detail

vDReg

refactor

Compiler Update

Correct incorrect definitions of Blackhole __builtin_rvtt_sfpgt and __builtin_rvtt_sfple builtins.
Other compiler cleanups.

Compiler update

• Do not enable load-locked/store-conditional instructions on quasar (use the zaamo extension, rather than a)
• Do not enable floating point on quasar (no f extension)
• Correct a bug introduced renaming xttrocc to xttroccqsr, sorry
• Use #!/bin/env bash in shell scripts (thanks @iharabukhouski)

The vector, v, and compressed, c, extensions are already not enabled on quasar.

Quasar updates

Assembler Changes

• xttrocc ISA extension renamed xttroccqsr, for future proofing
• xttcache ISA extension added, this enables 2 cache control instructions

Compiler Changes

• -mcpu=tt-qsr64 enables xttcache extension
• -mcpu=tt-qsr64-rocc enable xttcache and renamed xttroccqsr extensions
• Wormhole, Blackhole ebreak erratum workaround added. Enabled by any -mcpu=tt-wh or -mcpu=tt-bh cpu selection,
• Crash in replay optimization fixed. This was caused by erroneous code that now (later) triggers a diagnostic as expected.

The ebreak workaround adds 8 nop instructions after any inline asm consisting of exactly ebreak. Embedding ebreak within a sequence of instructions will not invoke the workaround.

Compiler builtins change

The tensix builtins are not consistent in their parameter ordering. This reordered the few oddly ordered ones. Most users will not perceive a change as these are for internal use in the SFPI headers themselves.

• sfpsetman, sfpsetexp, sfpsetsgn (both _v and _i variants)
• sfpload, sfpstore
• sfpdivp2
• sfpstochrnd (both _v and _i variants)
• sfpxloadi

The changes:
a) move all the vector input operands to the beginning
b) place any operand that is permitted to be runtime-computable immediately after that.

It is not recommended that you start using these builtins directly. If you have use the above, you will need to update your code. The failure mode for not doing so will be compilation errors.

This removes a set of inconsistencies in the compiler.

Quasar pseudo-instructions

• Split quasar sfpload, sfpstore address operand to Dest/SrcS field and address:

 sfpload Reg,Addr,Mode,Mod1,Dest-or-SrcS,BankDone
 sfpstore Reg,Addr,Mode,Mod1,Dest-or-SrcS,BankDone

• Add sfpbankdone pseudo-instruction, which maps onto the sfpnop encoding with at least one non-zero operand:

sfpbankdone srcs_wr_done, srcs_rd_done, dest_done

An sfpbankdone instruction with 3 zero operands will disassemble to sfpnop.

• sfpnop returns to a non-operand instruction, as nops are meant to be:

sfpnop

• Swap address and register operands for sfpstore on all variants, to be more standard in how load and store instruction operand are ordered:

  sfpstore Reg,Addr,Mode,Mod1