Hardware_setup
Each FPGA loses its memory every time we disconnect the power. A goldfish will have longer memory compared to an FPGA. So in this sense, we have to reprogram the FPGA every time before we use it.
On the main OK FPGA, this is done in the software (when you start the Pulser server). However, the DDS boards are a bit more independent. There is a EEPROM programming chip which automatically programs the FPGA after the power is on.
Once we order a complete DDS board, we need to program them.
There are 2 10-pin connector on the DDS boards: JTAG and Active-Serial. JTAG is for quick testing of the FPGA. We want to program the EEPROM chip using Active-Serial programming. We do this using Quartus Software from Altera.
The picture below shows how to connect a USB-blaster to a DDS board for programming.
The RF amplitude of each DDS board is controlled by the variable-gain-amplifier. Normally, the control voltage is generated by a high-speed DAC on the board. The output range of this DAC is 0-1.2 V. However, the control voltage can be up to 1.4 V, which is the maximum of the VGA. In some application, we might need only a constant drive at the highest possible power, so we put this as an option.
There is this jumper shown in the picture below.
The pins configuration is an inverted-T. The top pad is ground. Center pad is the signal to the VGA. Left is the output from the DAC (so jump the center pin to this pin if you want regular tuning of the amplitude, as shown in the picture). The right pad is a fixed 1.4 V. So jump the center pin to the right will have the VGA always at the highest gain. So you can either turning on or off but not tune the amplitude.
Leaving the center pin unconnected will probably have the effect of max gain.