@@ -223,14 +223,16 @@ bool createXtensaPSRAMCacheFix::xtensaPSRAMCacheFixMemwReorg(
223223 case Xtensa::L16UI:
224224 case Xtensa::L8UI:
225225 if (StoreInsn) {
226- MachineMemOperand *MMO = *MII->memoperands_begin ();
227- if (!MMO->isVolatile ()) {
228- DebugLoc dl = MII->getDebugLoc ();
229- const MCInstrDesc &NewMCID = XtensaII->get (Xtensa::MEMW);
230- BuildMI (MBB, MII, dl, NewMCID);
231- Modified = true ;
232- StoreInsn = nullptr ;
233- NumAdded++;
226+ if (!MII->memoperands_empty ()) {
227+ MachineMemOperand *MMO = *MII->memoperands_begin ();
228+ if (!MMO->isVolatile ()) {
229+ DebugLoc dl = MII->getDebugLoc ();
230+ const MCInstrDesc &NewMCID = XtensaII->get (Xtensa::MEMW);
231+ BuildMI (MBB, MII, dl, NewMCID);
232+ Modified = true ;
233+ StoreInsn = nullptr ;
234+ NumAdded++;
235+ }
234236 }
235237 }
236238 if (LastHIQIStore) {
@@ -251,9 +253,11 @@ bool createXtensaPSRAMCacheFix::xtensaPSRAMCacheFixMemwReorg(
251253 } break ;
252254 case Xtensa::S16I:
253255 case Xtensa::S8I: {
254- MachineMemOperand *MMO = *MII->memoperands_begin ();
255- if (!MMO->isVolatile ()) {
256- LastHIQIStore = MI;
256+ if (!MII->memoperands_empty ()) {
257+ MachineMemOperand *MMO = *MII->memoperands_begin ();
258+ if (!MMO->isVolatile ()) {
259+ LastHIQIStore = MI;
260+ }
257261 }
258262 StoreInsn = MI;
259263 } break ;
@@ -292,13 +296,15 @@ bool createXtensaPSRAMCacheFix::xtensaInsertMemwReorg(MachineFunction &MF) {
292296 case Xtensa::L16SI:
293297 case Xtensa::L16UI:
294298 case Xtensa::L8UI: {
295- MachineMemOperand *MMO = *MII->memoperands_begin ();
296- if (!MMO->isVolatile () && (!HadMemw)) {
297- DebugLoc dl = MII->getDebugLoc ();
298- const MCInstrDesc &NewMCID = XtensaII->get (Xtensa::MEMW);
299- BuildMI (MBB, MII, dl, NewMCID);
300- Modified = true ;
301- NumAdded++;
299+ if (!MII->memoperands_empty ()) {
300+ MachineMemOperand *MMO = *MII->memoperands_begin ();
301+ if (!MMO->isVolatile () && (!HadMemw)) {
302+ DebugLoc dl = MII->getDebugLoc ();
303+ const MCInstrDesc &NewMCID = XtensaII->get (Xtensa::MEMW);
304+ BuildMI (MBB, MII, dl, NewMCID);
305+ Modified = true ;
306+ NumAdded++;
307+ }
302308 }
303309 HadMemw = false ;
304310 } break ;
@@ -307,13 +313,15 @@ bool createXtensaPSRAMCacheFix::xtensaInsertMemwReorg(MachineFunction &MF) {
307313 case Xtensa::S32I:
308314 case Xtensa::S16I:
309315 case Xtensa::S8I: {
310- MachineMemOperand *MMO = *MII->memoperands_begin ();
311- if (!MMO->isVolatile ()) {
312- DebugLoc dl = MII->getDebugLoc ();
313- const MCInstrDesc &NewMCID = XtensaII->get (Xtensa::MEMW);
314- BuildMI (MBB, NextMII, dl, NewMCID);
315- Modified = true ;
316- NumAdded++;
316+ if (!MII->memoperands_empty ()) {
317+ MachineMemOperand *MMO = *MII->memoperands_begin ();
318+ if (!MMO->isVolatile ()) {
319+ DebugLoc dl = MII->getDebugLoc ();
320+ const MCInstrDesc &NewMCID = XtensaII->get (Xtensa::MEMW);
321+ BuildMI (MBB, NextMII, dl, NewMCID);
322+ Modified = true ;
323+ NumAdded++;
324+ }
317325 }
318326 HadMemw = true ;
319327 } break ;
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