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Add USB OTG High-Speed on STM32H7S78-DK #9

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Add USB OTG High-Speed on STM32H7S78-DK #9

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48211c3
dts: arm: stm32h7rs: add USB OTG HS
titouanc May 9, 2025
5065f03
boards: st: stm32h7s78_dk: add support for OTGHS on USB1
titouanc May 9, 2025
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6 changes: 6 additions & 0 deletions boards/st/stm32h7s78_dk/stm32h7s78_dk.dts
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Expand Up @@ -185,6 +185,12 @@
status = "okay";
};

usb1: &usbotg_hs {
pinctrl-0 = <&usb_otg_hs_dm_pm5 &usb_otg_hs_dp_pm6>;
pinctrl-names = "default";
status = "okay";
};

usb2: &usbotg_fs {
pinctrl-0 = <&usb_otg_fs_dm_pm12 &usb_otg_fs_dp_pm11>;
pinctrl-names = "default";
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21 changes: 21 additions & 0 deletions dts/arm/st/h7rs/stm32h7rs.dtsi
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Expand Up @@ -790,6 +790,27 @@
<&rcc STM32_SRC_HSI48 OTGFS_SEL(0)>;
status = "disabled";
};

usbotg_hs: usb@40040000 {
compatible = "st,stm32-otghs";
reg = <0x40040000 0x40000>;
interrupts = <91 0>;
interrupt-names = "otghs";
num-bidir-endpoints = <9>;
ram-size = <DT_SIZE_K(4)>;
maximum-speed = "high-speed";
phys = <&usbphyc1>;
clocks = <&rcc STM32_CLOCK(AHB1, 25U)>;
status = "disabled";
};
};

usbphyc1: usbphyc@4000ec00 {
compatible = "st,stm32-usbphyc";
reg = <0x4000ec00 0x400>;
clocks = <&rcc STM32_CLOCK(AHB1, 26U)>,
<&rcc STM32_SRC_HSE USBPHYC_SEL(0)>;
#phy-cells = <0>;
};

otgfs_phy: otgfs_phy {
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1 change: 1 addition & 0 deletions include/zephyr/dt-bindings/clock/stm32h7rs_clock.h
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Expand Up @@ -75,6 +75,7 @@
#define SDMMC_SEL(val) STM32_DT_CLOCK_SELECT((val), 1, 2, D1CCIPR_REG)
#define XSPI1_SEL(val) STM32_DT_CLOCK_SELECT((val), 3, 4, D1CCIPR_REG)
#define XSPI2_SEL(val) STM32_DT_CLOCK_SELECT((val), 3, 6, D1CCIPR_REG)
#define USBPHYC_SEL(val) STM32_DT_CLOCK_SELECT((val), 3, 12, D1CCIPR_REG)
#define OTGFS_SEL(val) STM32_DT_CLOCK_SELECT((val), 3, 14, D1CCIPR_REG)
#define ADC_SEL(val) STM32_DT_CLOCK_SELECT((val), 3, 24, D1CCIPR_REG)
#define CKPER_SEL(val) STM32_DT_CLOCK_SELECT((val), 3, 28, D1CCIPR_REG)
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