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@pu-cc pu-cc commented Jul 10, 2025

This PR simplifies the handling of bypass bits with multiple GateMate FPGAs in JTAG chains.

Tested with A1, A2 and various combinations of JTAG chains as well as with the official and the Olimex evaluation kits.

@trabucayre trabucayre merged commit 5e91e20 into trabucayre:master Jul 10, 2025
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Applied. Thanks @pu-cc !

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2 participants